The Project | Content | Project Options command opens the Project Options dialog, which enables you to control the online availability of projects, define the reporting levels, establish connectivity, define which types of differences to find, and add parameters, among other options. The command is accessed from the schematic and PCB editors.
Schematic editor
PCB editor
The dialog can also be accessed by right-clicking on the project entry in the Projects panel then click Project Options from the context menu.
Use Set To Installation Defaults to set all options to the installation defaults.
For information about access and the options available on each of the tabs, see the drop-downs below.
This tab of the Project Options dialog enables you to define the reporting levels for each of the possible electrical and drafting violations that can exist on source schematic documents when validating the project. When the project is validated, these violation settings will be used in conjunction with the settings on the Connection Matrix tab to test the source documents for violations.
Validation of a project is performed using the Validate command available for the active project by choosing Project | Validation | Validate or from the right-click menu for a project from the Projects panel.
Violations List
This list presents all possible electrical and drafting violations that can exist on the source documents of the project. Violations themselves are gathered into the following categories:
Each specific violation type is presented with the following fields:
- Violation Type Description - a short description of the type of violation.
- Report Mode - use this field to specify the severity level associated with violating the check. Use the drop-down to choose from the following reporting levels:
Right-click Menu
The following commands are available from the right-click menu:
- All Off - set the Report Mode for all violation types to No Report.
- All Warning - set the Report Mode for all violation types to Warning.
- All Error - set the Report Mode for all violation types to Error.
- All Fatal - set the Report Mode for all violation types to Fatal Error.
- Selected Off - set the Report Mode for all selected violation types to No Report.
- Selected To Warning - set the Report Mode for all selected violation types to Warning.
- Selected To Error - set the Report Mode for all selected violation types to Error.
- Selected To Fatal - set the Report Mode for all selected violation types to Fatal Error.
- Default - set the Report Mode for all violation types back to their default settings.
Multiple violation types can be selected using standard multi-select techniques (Ctrl+Click, Shift+Click).
Additional Option
Enable the Report Suppressed Violations in Messages Panel to display violations in the Messages panel even if they have been suppressed through this tab.
Notes
This tab of the Project Options dialog delivers a matrix providing a mechanism to establish connectivity rules between component pins and net identifiers, such as Ports and Sheet Entries. It defines the logical or electrical conditions that are to be reported as warnings or errors. For example, an output pin connected to another output pin would normally be regarded as an error condition, but two connected passive pins would not.
Validation of a project is performed using the Validate command available for the active project by choosing Project | Validation | Validate or from the right-click menu for a project from the Projects panel.
The matrix presents all possible wiring connection checks between combinations of pins, ports, and sheet entries, as well as testing for unconnected entities. The matrix is read in an across/down fashion and the color of the matrix element at the row-column intersection specifies how the Compiler will respond when testing for that particular condition.
To change the reporting mode for a violation check in the matrix, click on the colored square where the row and column of two entities intersect. Each time you click, the mode will move to the next report level.
As you hover over a square, text is displayed below the matrix to describe the connectivity violation and the reporting mode in force.
Right-click Menu
The following commands are available from the right-click context menu:
- All Off - set all entries in the matrix to No Report.
- All Warning - set all entries in the matrix to Warning.
- All Error - set all entries in the matrix to Error.
- All Fatal - set all entries in the matrix to Fatal Error.
- Default - set all entries in the matrix back to their default settings.
Notes
- Use the Error Reporting tab to specify reporting levels associated with further electrical and drafting violations.
- There may be points in the design that you know will be flagged as electrical violations that you do not want to be flagged. To suppress these, place a No ERC schematic design directive object at each point.
The Comparator tab of the Project Options dialog enables you to define which types of differences to find and which to ignore when comparing documents. For each possible comparison, you can choose to either find or ignore differences using the associated drop-down in the Mode column. You can set up to find differences with components, nets, parameters, and physical objects as required.
Comparison Type Description/Mode
Additional Control
The Ignore Rules Defined in PCB Only option is used to ignore rules defined in the PCB only within the design project. For instance, when you do an engineering order change, changes can be applied from schematic to PCB and if this option is enabled, the rules in PCB only are ignored. If there are no corresponding rules in schematic sheets of the same project, then the comparator will not try to add new rules.
This tab of the Project Options dialog enables you to specify the output path and related options for generated outputs for the project. You can also specify various netlisting options and the Net Identifier Scope.
- Output Path - the default output path for the generation of output files from the current design project (*.PrjPcb).
- ECO Log Path - the default output path for ECO log files.
Output Options
- Open outputs after compile - enable to open files that were generated after compiling the design project.
- Timestamp folder - enable to create a timestamp folder for generated output. The folder name is in the format <FolderName> Date Time where the <FolderName> is specified in the Output Path field and Date and Time are in the same format as your system settings.
- Archive project document - enable to archive the project document.
- Use separate folder for each output type - enable to create separate folders for each output type generated for the design project. If you have opted to create a timestamp folder, separate folders will be created under that folder.
Netlist Options
- Allow Ports to Name Nets - enable to name a net using the Name property of a wired port rather than using a default, system-generated net name.
- Allow Sheet Entries to Name Nets - enable to name a net using the sheet entry name rather than using a default, system-generated net name.
- Allow Single Pin Nets - enable to allow the existence of nets containing only a single pin.
-
Append Sheet Numbers to Local Net - enable to append the value for a schematic document's Sheet Number parameter (a document-level parameter) to nets that are local to that sheet. A local net is a net that does not leave the sheet. For a net that does leave the sheet (and is therefore not local), this option does not apply.
If the Net Identifier Scope option is set to Global, then all nets with the same net label will be connected together on all sheets. Since these nets are not local, the Append Sheet Numbers to Local Net option is not applied.
The Append Sheet Numbers to Local Nets option will work only if each schematic sheet has been assigned a unique SheetNumber. The SheetNumber parameter is assigned on the Parameters tab of the Inspector panel in Document Options mode for each schematic sheet.
- Higher Level Names Take Priority - enable to have the net labels used on higher sheets in the hierarchy name the nets on the lower sheets.
- Power Port Names Take Priority - the software has the ability to localize a global power net by wiring a power port to a normal port. This would force all pins on that sheet connected to that power port to be in a separate net. Enabling this option would force net naming using the name of the net assigned to the power port.
If only Higher Level Names Take Priority is enabled, the naming order of precedence is as follows: Net labels, power ports, ports, pins. However, if the Power Port Names Take Priority option is also enabled, then the naming order of precedence is: Power ports, net labels, ports, pins.
Net Identifier Scope
Multi-sheet designs are defined at the electrical (or connective) level by Net Identifiers. Net identifiers (net labels, ports, sheet entries, power ports, and hidden pins) create logical connections between points in the same net. This can be within a sheet or across multiple sheets. Physical connections exist when one object is attached directly to another electrical object by a wire. Logical connections are created when two net identifiers of the same type (e.g., two net labels) have the same Net property.
When the connectivity model of the design is created, you must define how you want net identifiers to connect to each other – this is known as setting the Net Identifier Scope. There are essentially two ways of connecting sheets in a multi-sheet design: either horizontally, directly from one sheet to another sheet to another sheet, etc., or vertically, from a sub-sheet to the sheet symbol that represents it on the parent sheet. In horizontal connectivity, the connections are from port to port (net label to net label is also available). In vertical connectivity, the connections are from sheet entry to port.
The scope of net identifiers should be determined at the beginning of the design process.
Use the drop-down to choose from the following scopes:
-
Automatic (Based on project contents) - this mode automatically selects which of the net identifier modes to use based on the following criteria: if there are sheet entries on the top sheet, then Hierarchical is used; if there are no sheet entries, but there are ports present, then Flat is used; if there are no sheet entries and no ports, then Global is used.
The Automatic mode defaults to use the standard Hierarchical mode if need be, with power ports connecting globally. To use Strict Hierarchical, manually set the Net Identifier Scope accordingly. Hidden pins are always deemed to be global.
- Flat (Only ports global) - ports connect globally across all sheets throughout the design. With this option, net labels are local to each sheet, i.e. they will not connect across sheets. All ports with the same name will be connected on all sheets. This option can be used for flat multi-sheet designs. It is not recommended for large designs as it can be difficult to trace a net through the sheets.
- Hierarchical (Sheet entry <-> port connections, power ports global) - connect vertically between a port and the matching sheet entry. This option makes inter-sheet connections only through sheet symbol entries and matching sub-sheet ports. It uses ports on sheets to take nets or buses up to sheet entries in corresponding sheet symbols on the parent sheet. Ports without a matching sheet entry will not be connected even if a port with the same name exists on another sheet. Net labels are local to each sheet, i.e. they will not connect across sheets. However, power ports are global – all power ports with the same name are connected throughout the entire design. This option can be used to create designs of any depth or hierarchy and allows a net to be traced throughout a design on the printed schematic.
- Strict Hierarchical (Sheet entry <-> port connections, power ports local) - this mode of connectivity behaves in the same way as the Hierarchical mode, with the difference being that power ports are kept local to each sheet, i.e. they will not connect across sheets to power ports of the same name.
- Global (Netlabels and ports global) - ports and net labels connect across all sheets throughout the design. With this option, all nets with the same net label will be connected together on all sheets. Also, all ports with the same name will be connected on all sheets. If a net connected to a port also has a net label, its net name will be the name of the net label. This option can also be used for flat multi-sheet designs, however, it is difficult to trace from one sheet to another since visually locating net names on the schematic is not always easy.
If the design uses sheet symbols with sheet entries, the Net Identifier Scope should be set to Hierarchical or Strict Hierarchical. In either of these modes, the top sheet must be wired. If not using sheet symbols with sheet entries, connectivity can be established via Ports and/or Net labels, therefore, one of the other two net identifier scopes (Flat or Global) should be used accordingly.
Remember that net labels do not connect to ports of the same name.
Allow Pin-Swapping Using These Methods
In the PCB editor, Pin, Differential Pair and Part swaps are performed by exchanging nets on component pads and their corresponding copper. When the changes are merged into the schematics, there are two ways that a pin swap can be handled:
- Adding / Removing Net-Labels - enable to allow swapping of pins on a component symbol. Performing the swap on the schematic by swapping net labels can only be done if the connectivity is established through the net labels, i.e. if the pins are not hardwired together.
-
Changing Schematic Pins - enable to allow swapping of net labels on the wires attached to the pins of a component. Swapping Pins will be the only option available when nets have been physically hardwired to a component. This method can be used on simple components (such as a resistor array) or where there is no alternative because of the structure of the schematic design.
Swapping the pins will always work on the schematic, but it may mean that the instance of the component symbol is no longer the same as it was defined in the library. In this situation, it means the symbol can no longer be updated from the library without destroying swapping information. It also means that other instances of the same component in this design will have a different pin arrangement, which could be a source of confusion to someone reading the schematic.
This tab of the Project Options dialog enables you to define the channel naming scheme and component designator format for use with multi-channel designs. Multi-channel design is the ability to reference the same sub-sheet in the project multiple times. This can be done by placing multiple sheet symbols that reference the same sub-sheet, or by including the Repeat keyword in the designator of a Sheet Symbol to instantiate it multiple times.
CircuitMaker offers true multi-channel design, meaning that you can reference single sheets repeatedly in a project. Any changes that might need to be made can be applied in one place and recompiling the project then propagates those changes through each instantiation.
The mapping from the single logical component on the schematic to the multiple physical instances on the PCB is controlled by the multi-channel designator scheme defined on this tab.
Channel Naming
Hierarchical channel names are formed by concatenating all channelized sheet symbol designators (ChannelPrefix + ChannelIndex) in the relevant channel path hierarchy.
- Channel Naming Style - use this field to specify the style that is to be used to name the channels. As you select a style from the list, the image below is updated to reflect the naming convention that will appear in the design. When the design is compiled, a channel is created for each sheet in the design, including each bank and each lower-level channel. There are five styles available — two flat and three hierarchical (those including path):
- Flat Numeric With Names
- Flat Alpha With Names
- Numeric Name Path
- Alpha Name Path
- Mixed Name Path
-
Level Separator for Paths - use this field to specify the required character/symbol for separating the path information when using the hierarchical naming styles (those styles that include the path). By default, the underscore character (_) will be used.
There is no restriction on the entry used for the level separator, although to retain visual clarity, it is advisable to keep it to a single non-alphanumeric character.
- Preview - as you make changes to the Room Naming Style and/or Designator Format, the image in this region dynamically updates to reflect the naming convention that will appear in the design. The image gives an example of a 2 x 2 nested channel design. The larger cross-hatch regions represent the two upper-level channels (or banks) and the shaded regions within represent the lower-level channels (with two sample components shown in each).
Component Naming
- Designator Format - use this field to specify the format used when assigning designators to the design components. Eight predefined formats are available from the field's drop-down list: five flat and three that can be used in a hierarchical context (containing the channel naming).
Notes
- The alpha indexing for a channel is only really useful if your design contains less than 26 channels in total or if you are using a designator format that is hierarchical in nature.
- You must recompile your project in order for any changes made to channel and/or component designator formats to take effect.
- When a multi-channel design is compiled, tabs are displayed along the bottom of the schematic sheet in the design window, one for each channel (or bank). The tab names are the sheet symbol names plus the channel number, e.g., BANKA. These are the compiled views (physical views) of the design, while the logical design remains as before on the Editor tab.
This tab of the Project Options dialog enables you to manage parameters defined for the project, often referred to as project-level parameters. Parameters defined at the project level are available for use across all schematic sheets and PCB documents in the project through the use of special strings (=<ProjectParameterName> on a schematic and .<ProjectParameterName> on a PCB). Parameters can be used to provide additional design information. Project parameters are saved in the project file (*.PrjPcb)
CircuitMaker supports parameters at various levels of the project - project-level parameters, document-level parameters (defined for a schematic sheet), and variant-level parameters. They also have a hierarchy, which means you can create a parameter with the same name at different levels of the project, each having different values. CircuitMaker resolves this with the following order of precedence: Variant (highest priority) ---> Schematic Document ---> Project (lowest priority). That means the parameter value defined in the schematic document overrides the value defined in the project options, and the value defined in the variant overrides the value defined in the schematic document. (Note that schematic-level parameters are not available on the PCB. For these types of outputs, use project or variant parameters.
Right-click Menu
The following commands are available on the right-click menu:
- Edit - use this command to modify the currently selected parameter in the Parameter Properties dialog.
- Add - use this command to add a new parameter to the list in the Parameter Properties dialog.
- Remove - use this command to delete the selected parameter(s) from the list.
- Copy - use this command to copy the selected parameter(s) to the Windows clipboard.
- Paste - use this command to paste parameter(s) on the Windows clipboard into the parameters list.
The Copy and Paste commands support the ability to define a set of parameters in an external spreadsheet (such as Microsoft Excel) and paste them into the tab. If a parameter being pasted has the same name as an existing parameter in the list, the value for the existing parameter will be overwritten with the one being pasted.
Use the following collapsible sections to access information on each violation available on the Error Reporting tab of the Project Options dialog.
Violations Associated with Components
Default report mode:
This violation occurs if a component has been soft deleted from the project after project validation
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
ComponentName: Component has been deleted,
where:
ComponentName is the name of the component in the source schematic library.
Recommendation for Resolution
The violation arises because a component has been soft deleted from the project after the project has been validated. If the component was soft deleted in error, replace the component.
Default report mode:
This violation occurs when compiling an Integrated Library Package (*.LibPkg) and the pin mapping between the schematic component and the linked model is found to be invalid.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
ComponentName: Could not find port <>ModelPinNumber on model <ModelName> for pin <ComponentPinNumber>,
where:
ComponentName is the name of the component in the source schematic library.
ModelPinNumber is the expected designator for the pin/pad that could not be found on the linked model.
ModelName is the name of the model that is linked to the component.
ComponentPinNumber is the designator of the pin on the source schematic component to which the erroneous pin of the model is mapped.
Recommendation for Resolution
The violation arises because the entry in the Model Pin Designator points to a pad designator that does not exist in the PCB model. Amend the entry as required. Typically, there will be one-to-one mapping with the designators on both sides the same.
Default report mode:
This violation occurs when the same part of a multi-part component instance has been placed more than once in a schematic design. For example, you have placed a 74HC32 component with designator U9, but have inadvertently placed two instances of part one of this component, resulting in two instances of U9A in the design.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Component <ComponentName> has duplicate sub-parts at <Location1> and <Location2>,
where:
ComponentName is the name of the offending component in terms of its designator and library reference.
Location1 is the X,Y coordinates for the first instance of the particular sub-part.
Location2 is the X,Y coordinates for the duplicate instance of the particular sub-part.
Recommendation for Resolution
Change the part number for the offending parts as required. This can be achieved in one of the following ways:
- Access the Inspector panel for the part and change the part number.
- Use the Increment Part Number command, which is available from the Part Actions sub-menu (when right-clicking over the part).
Default report mode:
This violation occurs when two or more pins in a component have the same designator.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Duplicate pins in component Pin <Identifier1> and Pin <Identifier2>,
where:
Identifier1 is the identifier for the first instance of the duplicated pin, represented by the part designator-pin designator pairing
Identifier2 is the identifier for the second instance of the duplicated pin, represented by the part designator-pin designator pairing.
Recommendation for Resolution
Change the designator of the offending pin(s) accordingly, so that each has a unique assignment. Pin designators can be edited from within the schematic editor for a component that has already been placed. If the component pins are not locked, you can double-click on the pin and edit its designator in the Inspector panel. Otherwise, edit the pin(s) using the Component Pin Editor dialog.
Typically, the duplication will reside in the library component, in which case you should edit the pin designator for that component in the source schematic library then pass the change on to placed instances of the component using the Update Schematic Sheets command. This command is available from the right-click menu associated with the Components region of the SCH Library panel
Note
- Only one error instance will be listed in the Messages panel for each distinct component. A component may well have more than two pins with the same designator but when investigating the error using the Details region of the panel, only the first two duplicate pins (in alphabetical pin name order) will be listed.
Default report mode:
This violation occurs when at least two parts across source schematic sheets in a design have the same designator associated with them.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Duplicate Component Designators <PartDesignator> at <Location1> and <Location2>,
where:
PartDesignator is the offending designator.
Location1 is the X,Y coordinates marking the center of the parent part for the first instance of the offending designator.
Location2 is the X,Y coordinates marking the center of the parent part for the second instance of the offending designator.
Recommendation for Resolution
Assign different and unique designators to the duplicates as required. This can be done manually by editing each offending designator.
Alternatively, reset the duplicate component designators using the Tools | Annotation | Reset Duplicates command.
Default report mode:
This violation occurs if an extra pin has been detected in one of the display modes for a part.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Extra Pin <Identifier> in <DisplayMode> of part <PartName>,
where:
Identifier is used to identify the pin in question. When compiling a schematic library document, the identifier appears in the format PhysicalComponentName-PinDesignator (e.g., DIP14-15). When compiling the source schematic or project, the identifier appears in the format PartDesignator-PinDesignator (Inferred) (e.g., X1-1 (Inferred)).
DisplayMode is the specific graphical representation mode for the part in which the extra pin has been found. A part has a Normal mode and can have up to 255 defined Alternate modes
PartName is either the physical component name or the designator for the affected part, depending on whether you are compiling the schematic library document or source schematic sheet/project respectively.
Recommendation for Resolution
This violation typically arises when an alternate graphical mode is defined for a component and either:
- An extra pin has been added to the display that is not specified in the Normal display mode, or
- A pin has been specified with a different Designator and/or Name to a pin specified in the Normal display mode.
Not only must there be an identical number of pins between graphical display modes, but the pins must also be identical in both Designator and Name.
In the source schematic library, display the offending display mode for the component and delete the extra pin. Then pass the change on to placed instances of the component using the Update Schematic Sheets command. This command is available from the right-click menu associated with the Components region of the SCH Library panel.
Default report mode:
This violation occurs in multi-part components when a hidden pin common to more than one sub-part is connected to different nets.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Mismatched hidden pin connections in Pin <Identifier> and Pin <Identifier>
where
Identifier is used to identify the pin in question. The identifier appears in the format PhysicalComponentName-PinDesignator (e.g., U2-7).
Recommendation for Resolution
Reassign the offending pin(s) to the correct nets. Edit the pin(s) using the Component Pin Editor dialog. From the Component Pin Editor dialog, access the Logical tab of the Pin Properties dialog for the offending pin (for each sub-part in turn) and check/modify the net entry in the Connect To field.
Default report mode:
This violation occurs when compiling an Integrated Library Package (*.LibPkg) and a linked model for a component in the source schematic library could not be found.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in one of the following formats:
<ComponentName>: Could not find <ModelName> - when the model search scope is Any.
<ComponentName>: Could not find <ModelName> in <LibraryName> - when the model search scope is Library Name.
<ComponentName>: Could not find <ModelName> in <Path> - when the model search scope is Library Path.
where:
ComponentName is the name of the component in the source schematic library.
ModelName is the name of the 2D/3D Component model that is linked to the source component and could not be found.
LibraryName is the name of the library file specified to contain the linked model.
Path is the absolute path to a library file specified to contain the linked model.
Recommendation for Resolution
This issue is typically caused by one of the following scenarios:
- The model name is incorrectly specified when defining the model link.
- The linked model does not reside in the specified library file.
- The library file containing the linked model has been moved or deleted.
The format of the displayed error message depends on the search scope you have enabled when locating the model and can be of great help when tracking down the problem with the model link:
- If the model could not be found along a specified path (search scope: Library Path), ensure that the library file you have specified actually exists at that location and also check the library file to see if the model with the specified name exists within.
- If the model could not be found in a specified library file (search scope: Library Name), ensure that the library file has been added to the Available File-based Libraries list. Also, check to make sure the library file contains the model with the same name specified in the link.
- If the model could simply not be found (search scope: Any), ensure that a library file - containing a model with the same name as that specified in the link - has been added to the Available File-based Libraries list.
Default report mode:
This violation occurs if a pin is missing in one of the display modes for a part.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Missing Pin <Identifier> in <DisplayMode> of part <PartName>,
where:
Identifier is used to identify the pin in question. The identifier appears in the format PartLibraryReference-Pin Designator (e.g., DIP14-8)
DisplayMode is the specific graphical representation mode for the part in which the missing pin has been found. A part has a Normal mode and can have up to 255 defined Alternate modes
PartName is the library reference for the affected part.
Recommendation for Resolution
This violation typically arises when an alternate graphical mode is defined for a component, but not all pins specified in the Normal mode have been specified for the Alternate. Not only must there be an identical number of pins between graphical display modes, but the pins must also be identical in both Designator and Name.
In the source schematic library, copy the missing pins from an existing display mode into the offending display mode for the component. Then pass the change on to placed instances of the component using the Update Schematic Sheets command. This command is available from the right-click menu associated with the Components region of the SCH Library panel.
Default report mode:
This violation occurs when a sheet symbol contains two sheet entries possessing the same name.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Sheet Symbol with duplicate entries Sheet Entry <Identifier> at <Location1> and <Location2>,
where:
Identifier is used to represent the offending sheet entry. The identifier appears in the format SheetSymbolName-SheetEntryName(SheetEntryIOType).
Location1 is the X,Y coordinates for the first violating sheet entry.
Location2 is the X,Y coordinates for the second violating sheet entry.
Recommendation for Resolution
Change the name of the offending sheet entry object as required, either by editing the name in-situ or by double-clicking on the offending sheet entry and editing the Name field in the Inspector panel.
Default report mode:
This violation occurs when a component in the design is found to have a default designator (with a ? suffix) - either it has yet to be annotated or the designator has been reset.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Un-Designated Part <PartDesignator>,
where
PartDesignator is the default designator for the un-designated part (e.g., U?, D?, C?, etc.).
Recommendation for Resolution
Assign a unique designator to the offending component as required. This can be done manually by editing the designator or through use of the Annotate dialog (Tools | Annotation | Annotate).
Note
- Only one error instance will be listed in the Messages panel for each distinct designator type (U?, D?, C?, etc.). Multiple errors may exist.
Default report mode:
This violation occurs when a part of a multi-part component instance has not been used within the design. For example, three out of four parts for an instance of a 74HC32 component may have been placed and wired and the fourth has not.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Component <Identifier> has unused sub-part (<PartNumber>),
where
Identifier is the parent component, represented using the format Designator Library Reference (e.g., U11 74HC32)
PartNumber is an integer used to indicate which specific part is not being used (e.g., 1 represents part A, 2 represents part B, and so on).
Recommendation for Resolution
Place the unused part and connect its inputs to ground. To ensure the same root designator, copy an existing part for that component's instance and, after pasting, increment its part number accordingly.
Violations Associated with Documents
Default report mode:
This violation occurs when the link between a sheet symbol and a target schematic sub-document is invalid. This can occur when:
- A sheet symbol has been placed manually but no sub-level document reference has been entered into the symbol's Filename field.
- The document reference in the symbol's Filename field has been entered incorrectly - effectively targeting a document that does not exist.
- The referenced target document has been removed from the project or deleted.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Missing child-sheet in <SymbolFileName> in Symbol <SymbolDesignator>,
where:
SymbolFileName is the current entry for the parent sheet symbol's Filename field.
SymbolDesignator is the designator of the parent sheet symbol.
Recommendation for Resolution
Check the entry in the sheet symbol's Filename field. If the required target document already exists, ensure that the document name (including extension) is entered correctly into the field. If the target document has been removed from the project and you have access to it, add it back to the project. If the target document does not exist, right-click on the symbol then choose the Create Sheet From Sheet Symbol command from the Sheet Symbol Actions sub-menu.
Default report mode:
This violation occurs in hierarchical designs where two or more schematic sheets are at the top-level of the structure.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Multiple top level documents: <SheetName> has been used,
where:
SheetName is the name of the schematic document currently being used as the top-level sheet.
Recommendation for Resolution
This issue typically arises due to the sheet symbol on the true top sheet not targeting the intended sub-sheet correctly. To resolve this issue, first determine which schematic sheet is the intended sub-sheet. Check to see if a sheet symbol has been placed for the intended sub-sheet on the top-level schematic:
- If a sheet symbol does not exist, create it either by manual placement or by right-clicking on the sub-sheet then using the Sheet Actions » Create Sheet Symbol From Sheet command.
- If the sheet symbol exists, check the symbol's Filename field and ensure that it references the sub-sheet.
Upon recompiling, the hierarchy will be resolved and the error will disappear from the Messages panel.
Default report mode:
This violation occurs when a port on a child sheet is found not to be matched with a sheet entry on the parent sheet symbol. All sheet entries in the parent sheet symbol must be synchronized (matched) to corresponding ports on the child sheet.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Port <PortName> not matched to Sheet-Entry at <Location>,
where:
PortName is the name of the port on the child sheet.
Location is the X,Y coordinates for the port's electrical hotspot.
Recommendation for Resolution
This issue can arise for a number of reasons:
- The corresponding sheet entry for the port does not exist.
- The corresponding sheet entry for the port exists but with a different name.
- The corresponding sheet entry for the port exists but with a different I/O Type.
Use the Details region of the Messages panel to cross probe to the port in question, then Ctrl+double-click on the port to ascend to the parent sheet symbol. Right-click on the sheet symbol then choose Sheet Symbol Actions » Synchronize Sheet Entries and Ports from the menu that appears. This will give you access to the Synchronize Ports To Sheet Entries dialog for that sheet symbol.
Use the dialog to match the port in question to the required sheet entry. If the sheet entry does not exist, you can create it directly from the dialog. Where the sheet entry exists but the Name and/or I/O Type differ, you can determine, as part of the match, whether the Name and I/O Type to be used comes from the port or the sheet entry.
Note
- When the sheet entry and port exist but have different Names and/or I/O Types, there will be a corresponding error message stating that the sheet entry is not matched to a port. Synchronizing the sheet entry with the port will clear both errors.
Default report mode:
This violation occurs when a sheet entry is found not to be matched with a port on the child sheet referenced by the parent sheet symbol. All sheet entries in the parent sheet symbol must be synchronized (matched) to corresponding ports on the child sheet.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Sheet-Entry <SheetEntryName> not matched to Port at <Location>,
where:
SheetEntryName is the name of the sheet entry associated with the parent sheet symbol.
Location is the X,Y coordinates for the sheet entry's electrical hotspot.
Recommendation for Resolution
This issue can arise for a number of reasons:
- The corresponding port for the sheet entry does not exist.
- The corresponding port for the sheet entry exists but with a different name.
- The corresponding port for the sheet entry exists but with a different I/O Type.
Use the Details region of the Messages panel to cross probe to the sheet entry in question. Right-click on the parent sheet symbol then choose Sheet Symbol Actions » Synchronize Sheet Entries and Ports from the menu that appears. This will give you access to the Synchronize Ports To Sheet Entries dialog for that sheet symbol.
Use the dialog to match the sheet entry in question to the required port. If the port does not exist, you can create it directly from the dialog. Where the port exists but the Name and/or I/O Type differ, you can determine, as part of the match, whether the Name and I/O Type to be used comes from the sheet entry or the port.
Note
- When the sheet entry and port exist but have different Names and/or I/O Types, there will be a corresponding error message stating that the port is not matched to a sheet entry. Synchronizing the sheet entry with the port will clear both errors.
Default report mode:
This violation occurs when the project contains more than one schematic document with the same name in different folders.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:
Project <ProjectName> contains several documents named <SchematicDocumentName>
where:
- ProjectName is the name of the project associated with the error.
- SchematicDocumentName is the schematic document that has the same name as another schematic document(s) in the project.
Recommendation for Resolution
Save the offending schematic documents with a different name.
Violations Associated with Nets
Default report mode:
This violation is related to components and occurs when you have specified one or more pins to be hidden and connected to an existing net within the design - typically a power pin connected to VCC or GND, for example.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Adding items to hidden net <NetName>,
where
NetName is the name of the target net.
Recommendation for Resolution
The problem arises when the following properties for the offending pin(s) are evident:
- The Hide option is enabled.
- The Connect To field contains the specific power net name.
Resolution of this issue is on a per-component basis and also depends on whether a component contains multiple sub-parts.
For a non-multi-part component, enable the display of the pin(s) in the workspace (disable the Hide option). You will need to wire each pin to the appropriate power port for the net to which you want to connect.
The previous solution can also be applied to multi-part components, but a far better solution is to clear the Connect To field and set the Part Number field to 0. Leave the Hide option for the pin enabled. Repeat for each pin that has been connected to a power net in this way. Ideally, the power net connections should be assigned through use of part 0 in the source library component.
Default report mode:
This violation occurs when a net label has been detected to be floating - not attached to a wire or bus object - within the design. The message will also appear for a bus power port object that is not electrically connected to the rest of the circuit.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Floating Net Label <NetLabelName>,
where
NetLabelName is the name of the offending net label.
Recommendation for Resolution
Ensure that the offending net label object is connected to the required wire or bus object. If the net label is redundant, delete it from the design.
Check also that the wire/bus object and associated net label are on grid. An object can be moved back onto the grid manually, or by using the Tools | Arrange | Align » Align To Grid command.
Also, check that a wire is really a wire and not a line object!
Default report mode:
This violation occurs when a power port object has been detected to be floating - not electrically connected to a component - within the design. For example, the power port may have been placed but is not yet wired up to the rest of the circuit.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Floating Power Object <NetName>,
where:
NetName is the name of the net associated with the floating power port object.
Recommendation for Resolution
Ensure that the offending power port object is connected to the circuit as required. If the power port is redundant, delete it from the design.
Note
- This message is related to the standard, single-signal power port objects. A floating bus power port object will be flagged in the Messages panel as a Floating Net Label.
Default report mode:
This violation appears when a positive or negative polarity net has not been detected for a particular differential pair object within a design.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:
Missing Positive or Negative Net for differential pair <PairName>, positive/negative net <NetName>
where:
- PairName is the name of the differential pair for which a positive or negative polarity net has already been defined (e.g.,
V_RX1)
- NetName is the name of the positive or negative polarity net (e.g.,
V_RX1_P).
Recommendation for Resolution
This violation typically arises in the following situations:
- A differential pair directive has not been attached to the positive/negative polarity wire of the signal pairing. The required net label (e.g.,
V_RX1_P) has been attached to the wire as required.
- An appropriately-named net label (e.g.,
V_RX1_P) has not been attached to the positive/negative polarity wire of the signal pairing. The required differential pair directive has been attached to the wire as required.
To resolve this violation, locate the positive/negative wire object for the pair and ensure that both the net label and differential pair directive are attached and that the name of the net label is specified as required. The net label for the positive/negative wire will be essentially the same as that for the positive or negative wire.
Default report mode:
This violation occurs when a parameter set object is attached to a net object (wire or bus) and at least one of the defined classes in the set has no name/value assigned to it.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:
Invalid net-parameter name/value at <Location>
where:
- Location is the X,Y coordinates for the hotspot of the parameter set object associated with the net.
Recommendation for Resolution
Select the offending parameter set object in the workspace to access its properties in the Inspector panel. Ensure that all parameters defined in the Classes section of the panel have a name/value assigned to them. If the offending class parameter is not required, remove it from the set.
If the class parameter is visible in the design space, you can enter a name/value for it directly (click once to select, then click again to enter in-place editing), or select it to open the Inspector panel then enter a name/value for it.
Default report mode:
This violation occurs when an input pin for a placed part within the design has been detected to be floating, i.e. not electrically connected to any other part of the circuit.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Net <NetName> contains floating input pins (<PinList>),
where:
NetName is the name of the offending net.
PinList is the comma-separated list of pins in that net that are floating.
Recommendation for Resolution
This violation can arise in a number of situations. Consider the following when resolving a violation of this type:
- If the pin is not to be used within the design, either tie it to the appropriate power line (e.g.,
GND), or place a No ERC directive on it.
- Ensure that the wiring to the pin is making electrical contact - i.e. the wire or bus connects to the pin's electrical hot spot.
- Trace the connectivity of the parent net to which the offending pin is associated. Sometimes, a pin can be caused to 'float' when there is a break somewhere else in the net.
- Look for additional violation messages in the Messages panel that relate to the same parent net, especially those that mention unconnected objects - this can give an indication where the break in connectivity lies.
Default report mode:
This violation occurs when a net in the design has been detected to have multiple names associated with it.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Nets <Identifier> has multiple names (<NameList>),
where:
Identifier represents the type of connection and the name of the net. The connection can be one of the following:
- Wire - where the identifier will appear in the format
Wire NetName (e.g., Wire DTSA)
- Bus - where the identifier will appear in the format
Bus Slice NetName (e.g., Bus Slice A[0..7])
- Bus Element - where the identifier will appear in the format
Element[n]: NetPrefix (e.g., Element[0]: A)
NameList is a comma-separated list of all names found associated with the offending net. These names can come from attached net labels, sheet entries, power ports, and offsheet connectors.
Recommendation for Resolution
This violation can be resolved by ensuring that the names of all net identifiers associated with a particular net are the same. However, if you want to freely use multiple names with nets in your design and prevent related violation messages from appearing in the Messages panel, set the Report Mode for this violation type to No Report on the Error Reporting tab of the Project Options dialog (Project | Content | Project Options).
Default report mode:
This violation occurs when a net in the design has been detected to have no driving source. That is, the net does not include at least one pin with one of the following electrical types:
- IO
- Output
- Open Collector
- HiZ
- Emitter
- Power
It is not uncommon for a net to not include a pin of one of these types. For example, it can happen when:
- A net connects from a connector pin to an input pin.
- A net connects from a series passive component (that has passive pins) to an input pin.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Net <NetName> has no driving source (<PinList>),
where
NetName is the name of the offending net.
PinList is the comma-separated list of pins in that net.
Recommendation for Resolution
There are a number of different approaches to resolving this violation including:
- Edit the connector/passive component pin so that it is one of the electrical types listed above.
- Disable the Nets with No Driving Source violation check in the Error Reporting tab of the Project Options dialog (Project | Content | Project Options).
- Place a No ERC marker on the net (Home | Circuit Elements | Directives » Generic No ERC).
Default report mode:
This violation occurs when a net in the design has been detected to contain only one component pin.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Net <NetName> has only one pin (Pin <PinName>),
where:
NetName is the name of the parent net.
PinName is the component designator-pin designator identifier.
Recommendation for Resolution
By default, this message will not appear in the Messages panel. If you have enabled reporting for this violation type and want to resolve the issue, ensure that the offending net is wired to at least two component pins in the design.
Default report mode:
This violation occurs when two ports with the same name are detected on the same schematic sheet in the design.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Sheet contains duplicate ports Port <Identifier> at <Location1> and <Location2>,
where:
Identifier is the name of the offending port.
Location1 is the X,Y coordinates for the first instance of the particular port.
Location2 is the X,Y coordinates for the second instance of the port.
Recommendation for Resolution
With the violation selected in the Messages panel, use the Details region of the panel to quickly cross probe to the duplicate port objects. Determine which port object is in error and either rename it or delete it from the design.
Violations Associated with Others
Default report mode:
This violation occurs when an object is not aligned to the current Snap grid.
Notification
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic Compiler page of the System Preferences), an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:
Off grid <ObjectIdentifier> at <Location> ,
where:
ObjectIdentifier identifies the specific object that is currently off-grid. The identifier is composed of the object's type and its name/designator (e.g., Pin <PinDesignator>).
Location is the X,Y coordinates for the object's electrical hotspot.
Recommendation for Resolution
Ensure that the Snap grid is enabled on the Sheet Options tab of the Document Options dialog (Project | Content | Document Options). The offending object can be moved back onto the grid manually or by using the Tools | Arrange | Align » Align To Grid command.