Design Rules Available for PCB Layout in Altium Designer

This rule defines the minimum clearance allowed between any two primitive objects on a copper layer. Either a single value for clearance can be specified, or different clearances for different object pairings, through use of a dedicated Minimum Clearance Matrix. The latter, in combination with rule-scoping, provides the flexibility to build a concise and targeted set of clearance rules to meet even the most stringent of clearance needs.

Constraints

The rule scope returns a set of objects, the constraints detailed below are then applied to that set of objects:

• Connective Checking - the set of net objects returned by the rule scope can then be further narrowed down in the following ways:
  • Different Nets Only - constraint is applied between any two primitive objects belonging to different nets (e.g. two tracks on two different nets).
  • Same Net Only - constraint is applied between any two primitive objects belonging to the same net (eg, between a via and pad on the same net, or two track segments in the same net).
  • Any Net - constraint is applied between any two primitive objects belonging to any net in the design. This is the most comprehensive of the three options and covers the possibility of the objects belonging to the same net, or different nets.
  • Different Differential Pair - constraint is applied between any two primitive objects belonging to different nets of different differential pairs (e.g. a track in DiffPair1 and a track in DiffPair2). The rule does not apply between primitives in the two nets in the same differential pair (eg, DiffPair1_P and DiffPair1_N). Use this constraint to configure the clearance between the differential pairs.
  • Same Differential Pair - constraint is applied between any two primitive objects belonging to the different nets in the same differential pair (e.g. a track in TX_P and a track in TX_N). Use this constraint to configure the clearance when the nets in the differential pair must be closer together than allowed by the general clearance.

► Learn more about Differential Pair Clearance Checking

• Ignore Pad to Pad Clearances within a footprint - toggle this option on/off to specify whether clearances between pads in the same component footprint are ignored. This option is disabled by default.
• Minimum Clearance - the value for the minimum clearance required. A value entered here will be replicated across all cells in the Minimum Clearance Matrix. Conversely, when a different clearance value is entered for one or more object pairings in the matrix, the Minimum Clearance constraint will change to N/A, to reflect that a single clearance value is not being applied across the board.
• Minimum Clearance Matrix - provides the ability to fine-tune clearances between the various object-to-object clearance combinations in the design.

Working with the Clearance Matrix

For many users, there is no great difference between Track and Arc primitives. And when it comes to Fill, Region, and Polygon objects, most users just see these as more 'copper.' With this in mind, the minimum clearance matrix for the Clearance rule has been enhanced to operate in two modes:

• Simple - in this mode, Track and Arc objects (including Track Keepout and Arc Keepout objects) are combined into the single Track entry. Fill, Poly, and Region objects (including Fill Keepout and Region Keepout objects) are combined into the single Copper entry. The Simple mode is the default mode, regardless of whether opening an existing design or a new design.
• Advanced - this mode is the traditional matrix, present in previous versions of the software, with all objects presented.

Definition of clearance values in the matrix can be performed in the following ways:

• Single cell editing - to change the minimum clearance for a specific object pairing. Simply click on a cell to select it for editing.
• Multi-cell editing - to change the minimum clearance for multiple object pairings:
  • Use Ctrl+Click, Shift+Click, and Click+Drag to select multiple cells in a column.
  • Use Shift+Click, and Click+Drag to select multiple contiguous cells in a row.
  • Use Click+Drag to select multiple contiguous cells across multiple rows and columns
  • Click on a row header to quickly select all cells in that row.
  • Click on a column header to quickly select all cells in that column.

With the required selection made (either a single cell or multiple cells), making a change to the current value is simply a case of typing the new value required. To submit the newly entered value, either click away on another cell, or press Enter. All cells in the selection will be updated with the new value.

Example multi-cell editing. Notice that as different values for clearance now exist for one or more object pairings, the Minimum Clearance constraint has changed to N/A, to reflect that a single clearance value is no longer being applied for all object-to-object clearance combinations.

Hole-to-Object Clearance Checking

Designers can check clearances between the edges of drill holes and neighboring copper objects on signal layers. This is particularly beneficial in preventing the routing of track too near to a drilled hole, which could otherwise suffer from any potential wandering of the drill during board fabrication. The row at the bottom of the Clearance rule's minimum clearance matrix is used to define the desired clearances.

Set clearance values to catch any copper objects that are too close to the edges of drill holes in the design.

Split Plane Clearance Checking

Designers can also check clearances between split plane regions on internal plane layers. How clearance is defined depends on the mode in which you are using the minimum clearance matrix:

• Simple mode - specify the required split plane-to-split plane clearance value using the Copper-Copper cell.
• Advanced mode - specify the required split plane-to-split plane clearance value using the Region-Region cell.

A violation will appear in the form:

Clearance Constraint: (<CurrentClearance> < <DefinedClearance>) Between Split Plane (<NetName>) on <InternalPlaneLayerName> And Split Plane (<NetName>) on <InternalPlaneLayerName>,

for example:

Clearance Constraint: (32.36mil < 34mil) Between Split Plane (GND) on Internal Plane 1 And Split Plane (NetC6) on Internal Plane 1

Clearance checking between split plane regions on an internal layer. In this case, the clearance value of 34mil has been entered in the Region-Region cell, as clearances are being defined using the Advanced mode of the matrix.

Differential Pair Clearance Checking

Differential pairs present unique design challenges, often requiring a specific within-pair clearance as well as a pair-to-pair clearance, and potentially a third rule to control the pair-to-all other nets, clearance. To support this, the Constraints region includes the dropdown where you can choose Same Differential Pair and Different Differential Pair options.

For example, if the nets within the differential pairs require a tighter clearance than the general board clearance, this can be achieved by using the Same Differential Pair constraint option, as shown below. Note that even though the rule scope applies to All net objects in the design, the Constraint setting restricts it to only apply to objects in the Same Differential Pair.

This result could also be achieved by scoping the rule to only apply to differential pair objects (eg, InAnyDifferentialPair), as shown below. Note that this rule would also apply between a net in a differential pair to any other net object in the design, so this approach should only be used if you have other higher priority rule(s) that define the DiffPairNet-to-DiffPairNet and/or DiffPairNet-to-Any requirements. If this approach is used, the Priority of the differential pair rules must also be configured correctly, with the rule with a tighter clearance requirement having a higher priority.

A similar approach can be used to control the clearance between differential pairs. The image below shows how the Different Differential Pair constraint can be used to achieve this.

As with the previous example, it could also be achieved using the rule scope, instead of the Different Differential Pairs constraint. Remember that the rule priorities must be configured so the rule with the tighter clearance requirement has a higher priority.

To define a different clearance from a differential pair net to any other net object, the following rule could be used.

This could be further refined so that it only applies between differential pair objects and non-differential pair objects, as shown below.

► Learn more about scoping Differential Pair design rules

► Learn more about Differential Pair Routing

Rule Application

Online DRC, Batch DRC, interactive routing, autorouting, and during polygon placement.

Notes

• When defining the constraints for the rule, the Connective Checking option would typically be set to Different Nets Only. An example of when Same Net Only or Any Net could be used is to test for vias being placed too close to pads or other vias on the same net, or any other net.
• The minimum clearance matrix applies irrespective of the connective checking method specified. If different clearances are required between objects on the same net, to those defined for objects on different nets, be sure to define separate clearance rules as required to suit.
• The applicable use of the clearance matrix depends on the rule scoping. For example with scoping of ALL-ALL, all cells in the matrix are applicable (i.e. all possible object pairings). However, if scoping were set to IsVia-IsTrack, then only the single cell for the Via-Track object pairing would be applicable, and all other cells in the matrix left unused.
• When defining a clearance rule for a polygon, it is the primitives of the polygon that the rule is actually applied to, rather than the polygon itself. The keyword entry InPolygon (or InPoly) should be included in the Full Query in this case, instead of IsPolygon (or IsPoly). The specific polygon clearance rule must also be given a higher priority than any general clearance rule, if it is to have any effect.
• When using the Dielectric Shapes Generator (in Printed Electronics), in Auto mode, the dielectric shape is automatically expanded to satisfy the requirement of the applicable Clearance Constraint design rule.
• In Printed Electronics, net to net clearances are tested on all layers, not just the same layer.

This rule tests for short circuits between primitive objects on the copper (signal and plane) layers. A short circuit exists when two objects that have different net names touch.

Constraints

Allow Short Circuit - defines whether the target nets falling under the two scopes (full queries) of the rule can be short-circuited or not. If you require two different nets to be shorted together, for example when connecting two ground systems within a design, ensure that this option is enabled.

Rule Application

Online DRC, Batch DRC, and during autorouting.

Note

In a Printed Electronics design when different nets cross over on different layers, they are flagged as a short circuit. These cross-overs are isolated by placing a dielectric patch on a non-conductive layer.

This rule tests the completion status of each net that falls under the scope (full query) of the rule. If a net is incomplete then each completed section (sub-net) is listed along with the routing completion. The routing completion is defined as:

(connections complete / total number of connections) x 100

The PCB Editor's Design Rule Checking system typically sees a net as being routed if all nodes in that net (component pads) are connected through the use of net-aware design objects (tracks, arcs, pads, vias, and polygons). These objects are considered connected if they touch each other. However, while simply touching makes a perceived connection to the software, when it comes time to fabricate the board, the fragility of some of these 'connections' can cause critical issues, especially where the objects - for example two contiguous track segments, or a track entering a pad/via - are only slightly touching. Such connections are often referred to as 'Bad Connections', 'Poor Connections', or 'Incomplete Connections'. This rule can also be configured to test for such poor connections.

Constraints

Check for incomplete connections - with this option enabled, the following additional checks on connectivity between applicable design objects are made:

• Track/Arc to Track/Arc - checking that the centerlines, or centers of the ends of the connecting track/arc segments, coincide.
• Track/Arc to Via - checking that the centerline, or center of the end of a track/arc segment, is placed on the shape of the via.
• Track/Arc to Pad - checking that the centerline, or center of the end of the track/arc segment, is placed on the shape of the pad.
• Via to Pad - checking that the center of the via is placed on the shape of the pad.
• Via to Via - checking that the centers of the two vias coincide.
• Polygon to Track/Arc - checking that the center of the end of a track/arc segment is overlapped by the polygon.
• Polygon to Pad/Via - checking that the center of the Pad/Via is overlapped by the polygon.

Rule Application

Batch DRC.

Notes

• A poor connection will be flagged in the design space using the detailed violation marker, , with a corresponding message appearing in the Messages panel.
• Where applicable, a connection line will be drawn between unconnected objects in the net, with data regarding the un-routed net length reflected in the PCB panel (in Nets mode).
• Some split plane DRC checks require the Un-Routed Net rule to be Batch-enabled for them to work.
• In Printed Electronics, layer transitions do not require a via, the net analyzer will recognize that the net is not broken if a via is removed from a routed net. A board is defined as Printed Electronics when the Printed Electronics option is enabled in the Layer Stack Manager. Learn more about Printed Electronics.

This rule detects pins that have no net assigned and no connecting tracks.

Constraints

None

Rule Application

Online DRC and Batch DRC.

This rule detects polygons that are still shelved and/or have been modified, but have not yet been repoured.

Constraints

• Allow shelved - if enabled, all polygons that fall within the scope of this design rule, and that are currently shelved, will not be flagged as a violation.
• Allow modified - if enabled, all polygons that fall within the scope of this design rule, and that are currently modified but have not been repoured, will not be flagged as a violation.

Rule Application

Online DRC and Batch DRC.

This rule tests the creepage distance between the targeted signals across the board surface through unplated holes, cutouts, and around the board edge. 

Constraints

• Creepage distance – a rule violation is flagged when any point on the First Object is equal to or less than the distance from any point on the Second Object.
• Ignore Internal Layers – use this option to ensure the rule will only be applied to outer layers.
• Apply to Polygon Pour – use this option to apply the rule to scoped polygons.

Rule Application

Online DRC, Batch DRC, and during autorouting.

Notes

• The Creepage Distance rule is not enabled for Online or Batch design rule checking by default. Enable Online/Batch checking in the Design Rule Checker dialog (Tools » Design Rule Check, Electrical category).
• The display of rule violations may also need to be configured, Violation Details (localized violation information) and/or Violation Overlay (highlighting of the entire objects in violation) is enabled in the PCB Editor - DRC Violation Display page of the Preferences dialog.
• The rule identifies the closest points on the targeted nets and checks the distance between them in the X, Y, and Z planes.
• If a board slot has been created by placing a pad, make sure that the Plated option is disabled in the pad properties as the software assumes that the plated barrel is conductive and will reduce the creepage distance accordingly.

This rule defines the width of tracks placed on the copper (signal) layers.

Constraints

• Preferred Width - specifies the preferred width to be used for tracks when routing the board.
• Min Width - specifies the minimum permissible width to be used for tracks when routing the board.
• Max Width - specifies the maximum permissible width to be used for tracks when routing the board.

• Check Tracks/Arcs Min/Max Width Individually - checks individual widths of tracks and arcs fall within the minimum and maximum range.
• Check Min/Max Width for Physically Connected - checks the width of routed copper formed by a combination of tracks, arcs, fills, pads, and vias falls within the minimum and maximum range.

• Use Impedance Profile - this option becomes available when there is at least one impedance profile defined in the Layer Stack Manager. When enabled, use the drop-down to select the impedance profile desired. When the rule is configured in this mode, the Preferred Width required on each routing layer is calculated as part of the specified impedance profile. Once the rule is defined, as you route a net that falls under the scope of the rule, the track width will automatically be set to the width required to meet the specified impedance for that layer. When this option is enabled the Preferred Width cannot be edited in the rule, but the Min Width and Max Width values can.

  ► Learn more about Configuring the Layer Stack for Controlled Impedance Routing

• Show values for layer stack - this option appears in the dialog when there are multiple layer stacks defined in the Layer Stack Manager. If the board includes multiple layer stacks then the Width Constraints must be configured for each of the layer stacks, using either the all-layer fields above the image or the layer-specific fields in the Layer Attributes Table.

  ► Learn more about Defining and Configuring Substacks

  ❯ ❮

  

  

  Javascript

  Configure the Constraints for each layer stack in the design.

• Layer Attributes Table - the grid region at the bottom of the dialog displays all signal layers defined in the layer stack, unless the Use Impedance Profile option is enabled. If this option is enabled, then only the layers available as part of the selected impedance profile will be displayed. The minimum, maximum and preferred routing widths are displayed, as well as other layer-specific information. The routing width fields can be set globally by defining the values in the constraint fields above the image, or individually by typing values directly into the table. When the Use Impedance Profile option is enabled, the required width entries will be automatically calculated and entered for each layer in the table. In this mode the Preferred Width values cannot be edited, but the Min Width and Max Width values can.

Rule Application

The Preferred Width setting is obeyed by the Autorouter.

The Min Width and Max Width settings are obeyed by the Online DRC and Batch DRC. They also determine the range of permissible values that can be used during interactive routing (press Tab key while routing to change the trace width within the defined range, through the Properties panel). If a value is entered outside of this range, it will automatically be clipped.

Note

The width of each net in a differential pair is monitored by the applicable Differential Pairs Routing rule.

This rule specifies the topology to be employed when routing nets on the board. The topology of a net is the arrangement or pattern of the pin-to-pin connections. By default, pin-to-pin connections of each net are arranged to give the shortest overall connection length. A topology is applied to a net for a variety of reasons; for high speed designs where signal reflections must be minimized the net is arranged with a daisy chain topology; for ground nets a star topology could be applied to ensure that all tracks come back to a common point.

Constraints

• Topology - defines the topology to be used for the net(s) targeted by the scope (full query) of the rule. The following topologies can be applied:
  • Shortest - this topology connects all nodes in the net to give the shortest overall connection length.
  • Horizontal - this topology connects all the nodes together, preferring horizontal shortness to vertical shortness by a factor of 5:1. Use this method to force routing in the horizontal direction.
  • Vertical - this topology connects all the nodes together, preferring vertical shortness to horizontal shortness by a factor of 5:1. Use this method to force routing in the vertical direction.
  • Daisy-Simple - this topology chains all the nodes together, one after the other. The order they are chained is calculated to give the shortest overall length. If a source and terminator pad are specified, then all other pads are chained between them to give the shortest possible length. Edit a pad to set it to be a source or terminator. If multiple sources (or terminators) are specified, they are chained together at each end.
  • Daisy-MidDriven - this topology places the source node(s) in the center of the daisy chain, divides the loads equally and chains them off either side of the source(s). Two terminators are required, one for each end. Multiple source nodes are chained together in the center. If there are not exactly two terminators the Daisy-Simple topology is used.
  • Daisy-Balanced - this topology divides all the loads into equal chains, the total number of chains equal to the number of terminators. These chains then connect to the source in a star pattern. Multiple source nodes are chained together.
  • Starburst - this topology connects each node directly to the source node. If terminators are present, they are connected after each load node. Multiple source nodes are chained together, as in the Daisy-Balanced topology.

Rule Application

During autorouting.

Note

When using the Autorouter, routing completion time may be longer when using topologies other than Shortest.

This rule assigns a routing priority to the net(s) targeted by the rule. The Autorouter uses the assigned priority value to gauge the routing importance of each net in the design and hence determine which nets should be routed first.

Constraints

Routing Priority - the priority value assigned to the net(s) targeted by the scope (full query) of the rule. Enter a value between 0 and 100, whereby the higher the number assigned, the greater the priority when routing.

Rule Application

During autorouting.

This rules specifies which layers are allowed to be used for routing.

Constraints

• Enabled Layers - each of the signal layers currently defined for the design, as defined by the layer stackup, are listed. Use the associated Allow Routing option to enable/disable routing on a layer, as required.

Rule Application

Online DRC, Batch DRC, during interactive routing, and while autorouting.

Note

When using the Autorouter, the routing direction for each enabled signal layer in the design is defined as part of the Situs Autorouter setup. Directions are specified in the Layer Directions dialog, accessed by clicking the Edit Layer Directions button in the Situs Routing Strategies dialog.

This rule specifies the corner style to be used during autorouting.

Constraints

• Style - specifies which routing corner style to use. The following three styles are available:
  • 90 Degrees.
  • 45 Degrees.
  • Rounded.
• Setback - these two fields allow you to define a minimum and maximum value for the setback, when using the 45 Degrees and Rounded corner styles. The setback is the distance from the 'true' corner location (that which would exist if using the 90 Degrees style) to the point at which the Autorouter should begin its chamfering or rounding, in effect controlling miter size or corner radius.

Rule Application

This rule is intended for use by third party Autorouters that implement 45° routing as a post process. It is not followed by the Situs Autorouter, which implements 45° routing as a native process.

This rule specifies the style of vias that can be used when routing. You have the option to define specific Min/Max/Preferred values for the via's diameter and hole size - defined as part of the rule's constraints - or use via templates available to the board design.

Constraints

• Mode - use the drop-down to choose from the following two modes:
  • Min/Max preferred - choose this mode to set the permissible values (Minimum/Maximum/Preferred) for the via's diameter and hole size as part of the rule itself.
  • Template preferred - choose this mode to be able to use via styles defined through via templates available to the board.

Mode = Min/Max preferred

When this mode is chosen, the constraints region changes to present the following options:

• Via Diameter - specifies constraint range values to be adhered to with respect to the diameters of vias placed when routing the board. The following individual values are definable:
  • Minimum - the minimum permissible value for the via diameter.
  • Maximum - the maximum permissible value for the via diameter.
  • Preferred - the preferred value for the via diameter.
• Via Hole Size - specifies constraint range values to be adhered to with respect to the hole sizes of vias placed when routing the board. The following individual values are definable:
  • Minimum - the minimum permissible value for the via hole size.
  • Maximum - the maximum permissible value for the via hole size.
  • Preferred - the preferred value for the via hole size.

Mode = Template preferred

When this mode is chosen, the constraints region changes to present the following options:

• Templates List - lists the available via templates that can be used with the rule. These are via templates (local or defined in Pad Via Template Libraries) that are made available to the board design as part of the Local Pad & Via Library (accessed through the PCB Pad Via Templates panel). For each available template the following information is presented:
  • Template Name - the read-only name of the template. For a local template, auto-generated naming is used, in compliance with IPC standards, For a template sourced from a PvLib, this naming can be customized as part of template configuration within that library.
  • Description - the read-only description written for the template.
  • Library - the library from which the template is sourced. This can be <Local> (where the via is defined and saved with the PCB document) or the name of the external Pad Via Template Library (<LibraryName>.PvLib) which has been made available to the PCB document.
  • Enabled - enable this option to have the template made available for via placement during Interactive Routing.

Rule Application

Online DRC, Batch DRC, during autorouting, during interactive routing.

When the mode of the rule is set to Min/Max preferred, the following considerations apply:

• The Preferred via attributes are used by the Autorouter.
• The Minimum and Maximum via attributes are obeyed by the Online DRC and Batch DRC.
• The Maximum and Minimum via attributes also determine the range of permissible values that can be used during interactive routing - when you press the + (or *) key on the numeric keypad to toggle routing signal layers and drop a via, press the / key on the numeric keypad to place a fanout via, or press the 2 shortcut key to place a via without changing layer.
• When a routing via is about to be placed during interactive routing, you can cycle through the Minimum / Preferred / Maximum / User Choice via definition by pressing the 4 key. The currently selected state is displayed in the Heads-Up Display, and on the Status bar. You can also press the Tab key while routing to access the Properties panel, from where you can edit the via properties within the Min/Max rule range. If a value is entered outside of its range, it will automatically be clipped.
• If there are multiple Via Types defined in the Layer Stack Manager, for example, thruhole and blind/buried vias, it can be possible for different Via Types to be used for the current layer transition. In this situation, press the 6 key to cycle through allowed Via Types. The selected Via Type is displayed in the Heads-Up Display, and on the Status bar. Alternatively, press the 8 key to display a pop-up menu of allowed Via Types, and click on the required one.

When the mode of the rule is set to Template preferred, the following considerations apply:

• When a routing via is about to be placed during interactive routing, you can cycle through the enabled via templates by pressing the 4 key. The selected template is displayed in the Heads-Up Display, and on the Status bar. You can also press the Tab key while routing to access the Properties panel, from where you can change the via template currently applied.
• If there are multiple Via Types defined in the Layer Stack Manager, for example, thruhole and blind/buried vias, it can be possible for different Via Types to be used for the current layer transition. In this situation, press the 6 key to cycle through allowed Via Types. The selected Via Type is displayed in the Heads-Up Display, and on the Status bar. Alternatively, press the 8 key to display a pop-up menu of allowed Via Types, and click on the required one.

Note

In order to control the size of blind and buried vias, individual rules can be set up targeting the different layer pairs. For example, to control the via size for blind vias between the top layer and mid layer 1, the following scope (Full Query) can be used:

(StartLayer = 'Top Layer') and (StopLayer = 'Mid-Layer1')

To control the via size for buried vias between mid layer 2 and mid layer 3, the following scope would be used:

(StartLayer = 'Mid-Layer2') and (StopLayer = 'Mid-Layer3')

Alternatively, instead of creating individual rules, you can expand the one rule query using ORs as follows:

((StartLayer = 'Top Layer') and (StopLayer = 'Mid-Layer1')) or((StartLayer = ' Mid-Layer2') and (StopLayer = 'Mid-Layer3'))

This rule specifies fanout options to be used when fanning out the pads of surface mount components in the design that connect to signal and/or power plane nets. Fanout essentially turns an SMT pad into a thru hole pad, from a routing point of view, by adding a via and connecting track. This greatly increases the probability of successfully routing the board, as a signal is made available to all routing layers instead of just the top or bottom layer. This is particularly needed in high-density designs where routing space is very tight.

Constraints

• Fanout Style - specifies how the fanout vias are placed in relation to the SMT component. The following options are available:
  • Auto - chooses the style most appropriate for the component technology and in order to give optimal routing space results.
  • Inline Rows - fanout vias are placed within two aligned rows.
  • Staggered Rows - fanout vias are placed within two staggered rows.
  • BGA - fanout occurs in accordance with the specified BGA Options.
  • Under Pads - fanout vias are placed directly under SMT component pads.
• Fanout Direction - specifies the direction to use for the fanout. The following options are available:
  • Disable - do not allow fanout with respect to the SMT components targeted by the rule.
  • In Only - fanout in an inward direction only. All fanout vias and connecting track will be placed within the component's bounding rectangle.
  • Out Only - fanout in an outward direction only. All fanout vias and connecting track will be placed outside of the component's bounding rectangle.
  • In Then Out - fanout all component pads in an inward direction to begin with. All pads that cannot be fanned out in this direction should be fanned out in an outward direction (if possible).
  • Out Then In - fanout all component pads in an outward direction to begin with. All pads that cannot be fanned out in this direction should be fanned out in an inward direction (if possible).
  • Alternating In and Out - fanout all component pads (where possible) in an alternating fashion, first inward then outward.
• Direction From Pad - specifies the direction to use for the fanout. When a BGA component is fanned out, its pads are sectioned into quadrants, with fanout applied to the pads in each quadrant simultaneously. The following options are available:
  • Away From Center - fanout for pads in each quadrant is applied following a 45° angle away from the component's center.
  • North-East - all pads, in each quadrant, are fanned out in a North-Easterly direction (45° anti-clockwise from the horizontal).
  • South-East - all pads, in each quadrant, are fanned out in a South-Easterly direction (45° clockwise from the horizontal).
  • South-West - all pads, in each quadrant, are fanned out in a South-Westerly direction (135° clockwise from the horizontal).
  • North-West - all pads, in each quadrant, are fanned out in a North-Westerly direction (135° anti-clockwise from the horizontal).
  • Towards Center - fanout for pads in each quadrant is applied following a 45° angle toward the component's center. In most cases, uniformity of direction will not be possible due to required fanout space already taken by another pads' fanout via. In these cases, fanout will occur in the next available direction (North-East, South-East, South-West, North-West).
• Via Placement Mode - specifies how the fanout vias are placed in relation to the pads of the BGA component. The following options are available:
  • Close To Pad (Follow Rules) - fanout vias will be placed as close to their corresponding SMT component pads as possible, without violating defined clearance rules.
  • Centered Between Pads - fanout vias will be centered between the SMT component pads.

Rule Application

During interactive routing and autorouting.

Notes

• The following default Fanout Control design rules are automatically created, covering the typical component package types available (listed in descending order of priority). These rules can be edited or others defined, in accordance with your individual design requirements.
  • Fanout_BGA – with a query of IsBGA.
  • Fanout_LCC - with a query of IsLCC.
  • Fanout_SOIC - with a query of IsSOIC.
  • Fanout_Small - with a query of (CompPinCount < 5).
  • Fanout_Default - with a query of All.
• The style used for the fanout vias will follow the applicable Routing Via Style design rule(s). Additional track laid down as part of the fanout process from pad to via will follow the applicable Routing Width design rule(s).
• To fanout the pads of a component, make sure that there is no polygon pours under this component on any layer. Polygons can be shelved before creating fanouts and restored afterward.

This rule defines the routing width of each net in a differential pair, and the clearance (or gap) between the nets in that pair. Differential pairs are typically routed with specific width-gap settings to deliver the required differential impedance needed for that net-pair.

► Learn more about Differential Pair Routing

► Learn more about Controlled Impedance Routing

Constraints

• Min Width - specifies the minimum permissible width to be used for tracks when routing the differential pair.
• Min Gap - specifies the minimum permissible clearance between primitives on different nets within the same differential pair. Gap settings are used as the differential pair is being routed, but not during rule checking, this requires a Clearance Constraint rule - refer to the Tips below for more information on how to manage this.
• Preferred Width - specifies the preferred width to be used for tracks when routing the differential pair.
• Preferred Gap - specifies the preferred clearance between primitives on different nets within the same differential pair.
• Max Width - specifies the maximum permissible width to be used for tracks when routing the differential pair.
• Max Gap - specifies the maximum permissible clearance between primitives on different nets within the same differential pair.
• Max Uncoupled Length - specifies the value for the maximum permissible uncoupled length between positive and negative nets within the differential pair.
• Use Impedance Profile - this option becomes available when there is at least one impedance profile defined in the Layer Stack Manager. When enabled, use the drop-down to select the required impedance profile. When the rule is configured in this mode, the Preferred Width and Preferred Gap required on each routing layer are calculated as part of the specified impedance profile. Once the rule is defined, as you route a differential pair that falls under the scope of the rule, the track widths and pair gap will automatically be set to the values required for that layer, to meet the specified impedance.
  ► Learn more about Configuring the Layer Stack for Controlled Impedance Routing
• Show values for layer stack - this option appears in the dialog when there are multiple layer stacks defined in the Layer Stack Manager. If the board includes multiple layer stacks then the Differential Pairs Routing Constraints must be configured for each of the layer stacks, using either the all-layer fields above the image or the layer-specific fields in the Layer Attributes Table.
  ► Learn more about Defining and Configuring Substacks
• Layer Attributes Table - the grid region at the bottom of the dialog displays all signal layers defined in the layer stack, unless the Use Impedance Profile option is enabled. If this option is enabled, then only the layers available as part of the selected impedance profile will be displayed. The minimum, maximum and preferred width and gap constraints are displayed, as well as other layer-specific information. The routing Width and Gap fields can be set globally by defining the values in the constraint fields above the image, or individually by typing values directly into the table. When the Use Impedance Profile option is enabled, the required width entries will be automatically calculated and entered for each layer in the table. In this mode the Preferred Width and Preferred Gap values cannot be edited, but the Min and Max values can.

Rule Application

Online DRC, Batch DRC, interactive routing (and re-routing), autorouting, interactive length tuning (Min Gap is applied), and when interactively modifying the pair, such as sliding a track segment of one of the nets in the pair.

Notes

• While the width of each net in a differential pair is monitored by the applicable Differential Pairs Routing rule (and not by a Width rule), clearance checking between the nets in that pair is still governed by the applicable Clearance design rule. In other words, a Clearance rule must be defined that targets the differential pair (on the specific layer where needed) with its connective checking mode set to Same Differential Pair, and whose clearance is set to be equal to, or lower than, the value for the Min Gap constraint defined for that layer as part of the applicable Differential Pairs Routing rule.
• The clearance from a net in a differential pair to any other electrical object that is not a part of the pair is monitored by the applicable Clearance rule.
• While the optimal width-gap settings may be achievable for most of the board, there will often be areas, such as under a BGA component, where smaller and tighter width-gap settings must be used. As well as switching the Width-Gap settings interactively, this requirement can also be achieved by defining multiple differential pair routing rules - a lower-priority rule that targets the differential pair across the board, and a higher-priority rule that targets the differential pair in specific areas. You then target the differential pair in a specific area by defining a Room Definition rule and use that room as part of the scope of a differential pair routing rule.
• Differential Pair classes, for use in rule scoping, can be defined on the schematic.

This rule specifies the minimum distance from the edge of a surface mount pad to the first routing corner.

Constraints

Distance - the value for the minimum permissible distance from the SMD pad edge to the start of the first routing corner.

Rule Application

Online DRC and Batch DRC, and Interactive Routing.

Notes

• The interactive router will obey this rule by maintaining a straight pad exit trace emanating from the pad center on any allowed "entry angle" (see SMD Entry rule), at least to the distance specified.

  
  The SMD to Corner rule defines the distance to the first corner. Use the SMD Entry rule to specify where the route is allowed to enter (or exit) the SMD pad.

• Once the pad has been exited, the route is kept away from the pad. The software does not allow the route to re-enter the pad and then re-exit without regard to the SMD rules.
• SMD rules are ignored if the pad exit is blocked (they are already ignored during pad entry in this situation). Note that if there is a pad exit available that does not violate the SMD to corner rule, that exit will be used.
• Miters are not created in violation of SMD rules. The software favors the SMD to corner rule over the miter, allowing the miter to collapse to zero if required.
• Stubs that follow the SMD rules are created in Any Angle routing mode. In this mode, once the first track segment has been placed arcs will be included in the corners. If you need an arc in the first corner, place the exit stub before attempting to create a corner.

This rule specifies the maximum routing length from the center of a surface mount pad to the center of the pad/via connecting to a power plane.

Constraints

Distance - the value for the maximum permissible distance from SMD pad to pad/via connecting to the power plane.

Rule Application

Online DRC and Batch DRC.

This rule specifies the maximum ratio of the track width to the SMD pad width, expressed as a percentage.

Constraints

Neck-Down - the percentage value for the maximum permissible ratio of track width to SMD pad width. Entering a larger value will allow for the use of greater width track.

Rule Application

Online DRC and Batch DRC.

This rule specifies the direction(s) a track can enter, or exit, an SMD pad.

Constraints

• Any Angle – if enabled, the track can enter/exit the pad at any angle, and at any point along its edge.
• Corner – if enabled, the track can enter/exit through a pad corner.
• Side – if enabled, the track can enter/exit at 90 degrees on either side of the pad. The longer edge of the pad is considered the side, note that the side option is only applied if the Side length > 2x End length. For example, if the pad is 2mm x 1mm then the side option is ignored (all sides are treated as ends). If the pad is 2.1mm x 1mm then the side option is applied.

Rule Application

Online DRC, Batch DRC, and Interactive Routing.

Notes

• The rule applies to surface mount pads only, that is, a pad defined on a single copper layer.
• The end of the pad is determined from the pad dimensions, the ends are the shorter edges.
• Pads can always be entered from either end (the shorter edge)
• The rule is applied on both routing out of the pad (exit) and into the pad (entry).

• The rule works in harmony with the SMD To Corner design rule, configure both to ensure neat SMD routing.

  
  The SMD Entry rule specifies where the route is allowed to enter/exit the SMD pad, all rule checkboxes are cleared in this example animation. Use the SMD to Corner rule to define the distance to the first corner.

• Once the pad has been exited, the route is kept away from the pad. The software does not allow the route to re-enter the pad and then re-exit without regard to the SMD rules.
• SMD rules are ignored if the pad exit is blocked (they are already ignored during pad entry in this situation). Note that if there is a pad exit available that does not violate the SMD to corner rule, that exit will be used.
• Miters are not created in violation of SMD rules. The software favors the SMD to corner rule over the miter, allowing the miter to collapse to zero if required.
• Stubs that follow the SMD rules are created in Any Angle routing mode. In this mode, once the first track segment has been placed arcs will be included in the corners. If you need an arc in the first corner, place the exit stub before attempting to create a corner.

The shape that is created on the solder mask layer at each pad and via site is the pad or via shape (or hole), expanded or contracted radially by the amount specified by this rule.

Constraints

• Expansion top - this constraint is used to specify the value applied to the initial pad/via shape (or hole) to obtain the final shape on the top solder mask layer.

• Expansion bottom - this constraint is used to specify the value applied to the initial pad/via shape (or hole) to obtain the final shape on the bottom solder mask layer.

  Use the  button to toggle between single, or separate expansions for the top and bottom sides of the board. When linked (), specify a value for the expansion in the Expansion top field. The Expansion bottom field will automatically inherit that same value. When unlinked (), you are free to specify different values for expansion, since the Expansion bottom field will become available to you for editing.
  Enter a positive value to expand the mask, enter a negative value to contract it.

• Solder Mask From The Hole Edge - use this constraint to determine the reference for the calculated mask expansion. When disabled, the perimeter of the object is used (the copper land edge for a pad or via). When enabled, the perimeter of the pad/via hole is used. For example, a 5mil Solder Mask Expansion applied to a 60mil diameter round pad will create a mask opening of 70mil (pad diameter + (2 x expansion)). If the reference is the hole edge, and the same pad had a hole diameter of 30mil, then the 70mil mask opening would be achieved by a 20mil expansion (hole diameter + (2 x expansion)).

  The significance of the Solder Mask From The Hole Edge option is that when enabled, the Solder Mask opening will follow the shape of the pad or via hole. The mask is therefore independent of pad shape and size, and is scaled from both the hole size and shape. So for example, a pad/via with a square hole will create a square mask opening that matches the hole dimensions, plus the assigned expansion value. Also note that a pad or via's expansion mask opening size will track any changes in the hole size.
• Tented
  • Top
    • Tented - check if it's desired for any solder mask settings in the solder mask expansion design rules to be overridden, which results in no opening in the solder mask on the top layer of this via and is therefore tented. You may disable this option, though the via will still be affected by a solder mask expansion rule or specific expansion value.
  • Bottom
    • Tented - check if it's desired for any solder mask settings in the solder mask expansion design rules to be overridden, which results in no opening in the solder mask on the bottom layer of this via and is therefore tented. You may disable this option, though the via will still be affected by a solder mask expansion rule or specific expansion value.

Rule Application

During output generation.

Notes

• Partial and complete tenting of pads and vias can be achieved by defining the appropriate value for the Expansion constraint:
  • To partially tent a pad/via (covering the land area only) – if the expansion is from the land pattern perimeter, set the Expansion to a negative value that will close the mask right up to the pad/via hole. If the expansion is from the hole edge, simply set the Expansion to be 0.
  • To completely tent a pad/via (covering the land and hole) – if the expansion is from the land pattern perimeter, set the Expansion to a negative value equal to, or greater than, the pad/via radius. If the expansion is from the hole edge, simply set the Expansion to be a negative value equal to, or greater than, the pad/via hole radius.
  • To tent all pads/vias on a single layer, set the appropriate Expansion value and ensure that the scope of the rule (the Full Query) targets all pads/vias on the required layer.
  • To completely tent all pads/vias in a design, in which varying pad/via sizes are defined, set the Expansion to a negative value equal to, or greater than, the largest pad/via radius.
• Solder mask expansion can be defined for pads and vias on an individual basis. While browsing properties for a pad or via through the Properties panel, options are available to follow the expansion defined in the applicable design rule, or to override the rule and apply a specified expansion directly to the individual pad or via in question. You can also force complete tenting of the pad/via on the top and/or bottom, using the Tented options in the Solder Mask Expansion section of the panel. When these options are disabled, the pad/via has no solder mask opening on the top/bottom of the board, and is therefore tented.
• These options correspond to the Solder Mask Tenting - Top and Solder Mask Tenting - Bottom properties for the pad when viewing properties through the PCB List panel.
• Solder mask expansion can also be defined at the individual level for the following objects (through the Properties panel, when browsing the properties of a selected object): Track, Region, Fill, Arc. Options are available to follow the expansion defined in the applicable design rule, to override the rule and apply a specified expansion directly to the individual object in question, or to have no mask at all.

The shape that is created on the paste mask layer at each pad site is the pad shape, expanded or contracted radially by the amount specified by this rule.

Constraints

• Expansion - the value applied to the initial pad shape to obtain the final shape on the paste mask layer.
• Measure Method - use this drop-down to specify the paste mask as an absolute expansion or as a percentage of the pad area. When the option is set to Percent, the Expansion is defined as a percentage of the pad area. You can set the Expansion as follows:
  • Expansion = 0 - the paste mask opening is the same size as the pad.
  • Expansion < 0 - enter a negative value to define a paste mask area that is <Value> percent smaller than the pad area.
  • Expansion > 0 - enter a positive value to define a paste mask area that is <Value> percent larger than the pad area.
• Use Paste - check the box to enable the chosen expansion value by default throughout all designs. The expansion value will be reflected in the Paste Mask Expansion region of the Pad Properties panel. Clear the checkbox to remove the paste from the targeted/selected pad(s). If this option is disabled, the expansion value will default to 0.

Rule Application

During output generation.

Notes

• The paste mask expansion can be defined for pads on an individual basis. While browsing properties for a selected pad through the Properties panel, options are available to follow the expansion defined in the applicable design rule, or to override the rule and apply a specified expansion directly to the individual pad in question.
• Paste mask expansion can also be defined at the individual level for the following objects (through the Properties panel, when browsing the properties of a selected object): Track, Region, Fill, Arc. Options are available to follow the expansion defined in the applicable design rule, to override the rule and apply a specified expansion directly to the individual object in question, or to have no mask at all.

This rule specifies the style of the connection from a component pin to a power plane.

Constraints

• Mode of Operation - the rule can operate in one of the following two modes:
  • Simple - this mode is the generic setting for how pads/vias connect to a power plane, as present in previous versions of the software.
  • Advanced - in this mode, you have the ability to define specific thermal connections for pads and vias, separately.
• Connect Style - defines the style of the connection from a pin of a component, targeted by the scope (Full Query) of the rule, to a power plane. The following three styles are available:
  • Relief Connect - connect using a thermal relief connection.
  • Direct Connect - connect using solid copper to the pin.
  • No Connect - do not connect a component pin to the power plane.

The following constraints apply only when using the Relief Connect style:

• Conductors - the number of thermal relief copper connections (2 or 4).
• Conductor Width - how wide the thermal relief copper connections are.
• Air-Gap - the width of each air gap in the relief connection.
• Expansion - the radial width measured from the edge of the hole to the edge of the air gap.

Rule Application

During output generation.

Notes

• The Simple mode is the default mode, for a newly created rule of this type.
• After setting and applying constraints in Advanced mode, be aware that switching back to Simple mode is considered a modification - clicking Apply or OK will effect the simple definition, overriding the individual advanced definitions specified previously.
• Power planes are constructed in the negative in the PCB Editor, so a primitive placed on a power plane layer creates a void in the copper.

This rule specifies the radial clearance created around vias and pads that pass through but are not connected to a power plane.

Constraints

Clearance - the value for the radial clearance.

Rule Application

During output generation.

This rule specifies the style of the connection from a component pad, or routed via, to a polygon plane.

Constraints

• Mode of Operation - the rule can operate in one of the following two modes:
  • Simple - this mode is the generic setting for how pads/vias connect to a polygon pour, as present in previous versions of the software.
  • Advanced - in this mode, you have the ability to define specific thermal connections for thru-hole pads, SMD pads, and vias, separately.
• Connect Style - defines the style of the connection from a pin of a component, targeted by the scope (Full Query) of the rule, to a polygon plane. The following three styles are available:
  • Relief Connect - connect using a thermal relief connection.
  • Direct Connect - connect using solid copper to the pin.
  • No Connect - do not connect a component pin to the polygon plane.

The following constraints apply only when using the Relief Connect style:

• Conductors - the number of thermal relief copper connections (2 or 4).
• Conductor Width - how wide the thermal relief copper connections are.
• Angle - the angle of the copper connections (45° or 90°).
• Air Gap Width - the distance between the edge of the pad and the surrounding polygon.

Rule Application

During polygon pour.

Notes

• The Simple mode is the default mode, for a newly created rule of this type.
• After setting and applying constraints in Advanced mode, be aware that switching back to Simple mode is considered a modification - clicking Apply or OK will effect the simple definition, overriding the individual advanced definitions specified previously.

The Fabrication Testpoint Style and Assembly Testpoint Style design rules specify the allowable physical parameters of pads and vias that are to be considered for use as testpoints for bare-board fabrication testing, or in-circuit assembly testing respectively. The constraints between these two rules are identical.

Constraints

Sizes

The following options allow you to specify pad/via diameter and hole size criteria when testing for valid testpoints:

• Min Size - specifies the minimum permissible diameter for a pad/via to be considered as a testpoint.
• Max Size - specifies the maximum permissible diameter for a pad/via to be considered as a testpoint.
• Preferred Size - specifies the diameter to be used for testpoint pads/vias placed by the Autorouter.
• Min Hole Size - specifies the minimum permissible hole size for a pad/via to be considered as a testpoint.
• Max Hole Size - specifies the maximum permissible hole size for a pad/via to be considered as a testpoint.
• Preferred Hole Size - specifies the hole size to be used for testpoint pads/vias placed by the Autorouter.

Clearances

The following options allow you to define clearance constraints specific to board testing:

• Min Inter-Testpoint Spacing - specifies the minimum permissable center-to-center distance to be observed between two adjacent testpoints, when considering a pad/via for use as a testpoint. This is typically determined by the probe head spacing for the flying probe, or bed-of-nails test fixtures, being used in the testing.
• Component Body Clearance - specifies the minimum permissable distance to be observed between a testpoint and the body of a component, when considering a pad/via for use as a testpoint. If a component has a component body, then the clearance is applied to the component body. If a component body is absent, then the clearance is applied to the component's non-pad/via primitive objects on the Mechanical + TopOverlay/BottomOverlay layers.
• Board Edge Clearance - specifies the minimum permissable distance to be observed between a testpoint and the edge of the board, when considering a pad/via for use as a testpoint.
• Distance to Pad Hole Centers - specifies the minimum permissable distance from the center of a testpoint, to the center of an adjacent pad (the center of the pad's hole).

• Distance to Via Hole Centers - specifies the minimum permissable distance from the center of a testpoint, to the center of an adjacent via (the center of the via's hole).

  The software checks the distance in accordance with the layer settings of the objects under test. For example, if a thru-hole pad is only configured to be a testpoint on the bottom layer, then the minimum clearance is not checked against other pads/vias on the top layer.

Grid

Use of a grid is most appropriate when targeting a non-custom bed-of-nails fixture. To include use of a grid, enable the Use Grid option. To disable use of a grid, enable the No Grid option.

If you do want to use a grid, the following options allow you to define it in a more comprehensive manner:

• Origin - the X and Y coordinates, specified relative to the current board origin. This allows you to align the grid with the origin of a bed-of-nails fixture.
• Grid Size - specifies the size of the grid to be used when attempting to find valid testpoint sites (pads and/or vias). If the entry is changed to zero, the No Grid option will automatically be selected upon applying the change.
• Tolerance - specifies the maximum permissable tolerance to use when considering how far from a specified grid a pad or via can be located and still be considered a valid testpoint location.

Allowed Side

Use these options to specify on which side of the board prospective testpoint pad/via locations can reside - either Top, Bottom, or both.

Allow Testpoint Under Component

Use this option to enable the use of pads/vias located underneath components (on the same side of the board as the components) for testpoint purposes. This option would typically be enabled in a Fabrication Testpoint Style rule, but not for an Assembly Testpoint Style rule - as the pad/via will typically not be accessible once the board is populated with components.

Rule Scope Helper

Use this region of the constraints to determine which objects the rule is to apply to. Simply enable the checkbox for the objects to be included - SMD Pads, Vias, Thru-hole Pads - and click on the Set Scope button. The logical query for the rule scope will be created and entered into the Full Query region for the rule.

Rule Application

This rule is obeyed by the Testpoint Manager, the Autorouter, the Online and Batch DRC, and during output generation. The Online DRC and Batch DRC test all attributes of the rule except the Preferred Size and Preferred Hole Size - these settings are used by the Autorouter to define the size of testpoint pads/vias that the Autorouter places.

Notes

• If you want to use a surface mount pad as a testpoint, the minimum hole size should be set to zero.
• When specifying use of a grid, if a pad/via assigned as a testpoint is not on the grid specified by the Grid Size option, it will cause a violation when performing a Design Rule Check (DRC). For example, if you set the Grid Size to 25mil, then the testpoints must be on a 25mil grid. If the testpoints do not lie on any particular grid, you can either enter a value for Grid Size that will accommodate all testpoints (the minimum setting is 0.001 mil), or you can simply specify the No Grid option.

The Fabrication Testpoint Style and Assembly Testpoint Style design rules specify the allowable physical parameters of pads and vias that are to be considered for use as testpoints for bare-board fabrication testing, or in-circuit assembly testing respectively. The constraints between these two rules are identical.

Constraints

Sizes

The following options allow you to specify pad/via diameter and hole size criteria when testing for valid testpoints:

• Min Size - specifies the minimum permissible diameter for a pad/via to be considered as a testpoint.
• Max Size - specifies the maximum permissible diameter for a pad/via to be considered as a testpoint.
• Preferred Size - specifies the diameter to be used for testpoint pads/vias placed by the Autorouter.
• Min Hole Size - specifies the minimum permissible hole size for a pad/via to be considered as a testpoint.
• Max Hole Size - specifies the maximum permissible hole size for a pad/via to be considered as a testpoint.
• Preferred Hole Size - specifies the hole size to be used for testpoint pads/vias placed by the Autorouter.

Clearances

The following options allow you to define clearance constraints specific to board testing:

• Min Inter-Testpoint Spacing - specifies the minimum permissable center-to-center distance to be observed between two adjacent testpoints, when considering a pad/via for use as a testpoint. This is typically determined by the probe head spacing for the flying probe, or bed-of-nails test fixtures, being used in the testing.
• Component Body Clearance - specifies the minimum permissable distance to be observed between a testpoint and the body of a component, when considering a pad/via for use as a testpoint. If a component has a component body, then the clearance is applied to the component body. If a component body is absent, then the clearance is applied to the component's non-pad/via primitive objects on the Mechanical + TopOverlay/BottomOverlay layers.
• Board Edge Clearance - specifies the minimum permissable distance to be observed between a testpoint and the edge of the board, when considering a pad/via for use as a testpoint.
• Distance to Pad Hole Centers - specifies the minimum permissable distance from the center of a testpoint, to the center of an adjacent pad (the center of the pad's hole).

• Distance to Via Hole Centers - specifies the minimum permissable distance from the center of a testpoint, to the center of an adjacent via (the center of the via's hole).

  The software checks the distance in accordance with the layer settings of the objects under test. For example, if a thru-hole pad is only configured to be a testpoint on the bottom layer, then the minimum clearance is not checked against other pads/vias on the top layer.

Grid

Use of a grid is most appropriate when targeting a non-custom bed-of-nails fixture. To include use of a grid, enable the Use Grid option. To disable use of a grid, enable the No Grid option.

If you do want to use a grid, the following options allow you to define it in a more comprehensive manner:

• Origin - the X and Y coordinates, specified relative to the current board origin. This allows you to align the grid with the origin of a bed-of-nails fixture.
• Grid Size - specifies the size of the grid to be used when attempting to find valid testpoint sites (pads and/or vias). If the entry is changed to zero, the No Grid option will automatically be selected upon applying the change.
• Tolerance - specifies the maximum permissable tolerance to use when considering how far from a specified grid a pad or via can be located and still be considered a valid testpoint location.

Allowed Side

Use these options to specify on which side of the board prospective testpoint pad/via locations can reside - either Top, Bottom, or both.

Allow Testpoint Under Component

Use this option to enable the use of pads/vias located underneath components (on the same side of the board as the components) for testpoint purposes. This option would typically be enabled in a Fabrication Testpoint Style rule, but not for an Assembly Testpoint Style rule - as the pad/via will typically not be accessible once the board is populated with components.

Rule Scope Helper

Use this region of the constraints to determine which objects the rule is to apply to. Simply enable the checkbox for the objects to be included - SMD Pads, Vias, Thru-hole Pads - and click on the Set Scope button. The logical query for the rule scope will be created and entered into the Full Query region for the rule.

Rule Application

This rule is obeyed by the Testpoint Manager, the Autorouter, the Online and Batch DRC, and during output generation. The Online DRC and Batch DRC test all attributes of the rule except the Preferred Size and Preferred Hole Size - these settings are used by the Autorouter to define the size of testpoint pads/vias that the Autorouter places.

Notes

• If you want to use a surface mount pad as a testpoint, the minimum hole size should be set to zero.
• When specifying use of a grid, if a pad/via assigned as a testpoint is not on the grid specified by the Grid Size option, it will cause a violation when performing a Design Rule Check (DRC). For example, if you set the Grid Size to 25mil, then the testpoints must be on a 25mil grid. If the testpoints do not lie on any particular grid, you can either enter a value for Grid Size that will accommodate all testpoints (the minimum setting is 0.001 mil), or you can simply specify the No Grid option.

This rule specifies the minimum annular ring required for a pad or via. The annular ring is measured radially, from the edge of the pad/via hole to the edge of the pad/via (also referred to as the land perimeter).

Constraints

Minimum Annular Ring (x-y) - the minimum value for the annular ring around the pads/vias targeted by the rule.

Rule Application

Online DRC and Batch DRC.

Notes

• Different fabrication houses will undoubtedly use varied and differing manufacturing technologies and equipment. Average performance houses may offer design specifications allowing a 10mil minimum annular ring. High performance houses may be able to reduce that figure down to 5mil. If pad and via holes are laser-drilled, as opposed to mechanically drilled, then the value for the minimum annular ring may be reduced further still.
• The class of board you are designing will also play a part in the value required for the minimum annular ring. For example, if your design is of IPC Class 3 standard, which refers to high reliability electronics products, the required minimum annular ring is 2mil.
• If you do have to reduce the annular ring below the accepted standard of the fabrication house, try to limit the usage of such affected pads and vias. The more pads and vias on the board that use such annular ring specifications, the more chance there is of a board failing during the fabrication process.
• To have no annular ring would, for one thing, cause poor solder joints, as there would be no copper for solder to flow onto after emerging from the pad/via barrel.
• Standards define a minimum value for the annular ring, but these values can be reduced further. The reason why they are defined at the levels they are, is to guard against drill breakout. This phenomenon is fairly common when dealing with low values for the annular ring. Drill breakout occurs as a result of several manufacturing parameters (e.g. hole location, hole size, film expansion) interacting unfavorably with one another, leading to the hole being drilled in such a position as to cut through the connecting copper track(s).
• It is possible to allow controlled drill breakout, without sacrificing board performance. One method of achieving this is to apply teardrops to required pads and vias. Teardropping (otherwise known as filleting, or tapering) is the process of applying additional land area to the pad/via at the junction with any connecting track(s). This additional area protects the pad-track (or via-track) connection should breakout occur.

• The Pad and Via objects with pad shapes removed by using the Unused Pad Shapes removal tool will not be reported as objects offending a Minimum Annular Ring design rule.

  
  The unused pad shapes have been removed from the inner layers for pads highlighted in the image (these pads have connections on the bottom layer only, the pad shape on the top layer is preserved to provide component solderability). While there are no pad shapes on these layers, these pads are not offending the Minimum Annular Ring design rule.

This rule specifies the minimum angle permitted between any objects in the same net. The Acute Angle rule works on nets only. It finds all the acute angles created by any objects in one net. The rule essentially creates a contour from all the primitives in a net (on the same layer) and then analyzes this contour for any points that might create an angle smaller then the acute angle limit value.

Constraints

• Minimum Angle - specifies the minimum permissible angle created between objects in the same net.
• Check Tracks Only - enable this option to force the DRC to check acute angles for track objects only.

Rule Application

Online DRC and Batch DRC.

This rule specifies the maximum and minimum hole size for pads and vias in the design. The hole size is the diameter of the hole to be drilled through the pad/via during fabrication.

Constraints

• Measurement Method - specifies the method used in defining the minimum/maximum hole sizes:
  • Absolute - the values for minimum/maximum hole sizes will be absolute values.
  • Percent - the minimum/maximum hole sizes will be expressed as percentages of the pad/via size.
• Minimum - the value for the minimum hole size with respect to pads and vias in the design. The value will appear as an absolute value (Default = 1mil) or percentage of the pad/via size (Default = 20%), depending on the measurement method selected.
• Maximum - the value for the maximum hole size with respect to pads and vias in the design. The value will appear as an absolute value (default = 100mil) or percentage of the pad/via size (Default = 80%), depending on the measurement method selected.

Rule Application

Online DRC and Batch DRC.

This rule checks to ensure that the used via types match the currently defined via types. The used via types are determined from the vias and pads found in the board. The permissible via types are defined on the Via Types tab of the Layer Stack Manager.

Constraints

Enforce layer pairs settings – specifies whether the check is made or not.

Rule Application

Online DRC, Batch DRC, and during interactive routing.

This rule ensures checking of manufacturing compatibility of drilled holes. When enabled, it will flag any multiple vias / pads at the same location, or overlapping pad / via holes. There is also an option to determine whether stacked micro vias are allowed or not.

Constraints

• Allow Stacked Micro Vias - enable this option to allow micro vias to be stacked.

  There are many advantages of using micro vias:

  • Such a via requires a much smaller pad, which helps to reduce the board size and weight.
  • They allow IC components to be more densely placed. This could result in the use of a smaller PCB, which would bring a welcome reduction in total board manufacturing costs.
  • They facilitate improved electrical performance, due to shorter pathways.

  Learn more about MicroVias

• Hole To Hole Clearance - the value for the minimum permissible clearance between pad/via holes in the design.

Rule Application

Online DRC and Batch DRC.

This rule helps identify narrow sections of solder mask that may cause manufacturing problems at a later stage. Ensuring that there is a minimum width of solder mask across the board, this rule checks that the distance between any two solder mask openings is equal to, or greater than, a user-specified minimum value. This includes the pads, vias, and any primitives that reside on solder mask layers. It also checks Top and Bottom sides independently.

Constraints

Minimum Solder Mask Sliver - specifies the minimum allowed width of solder mask.

Rule Application

Online DRC and Batch DRC.

This rule checks the clearance between any silkscreen primitive and any solder mask primitive, or exposed copper-layer primitive (exposed through openings in the solder mask). The check ensures that the distance is equal to, or greater than, the value specified in the constraint.

Many manufacturers routinely strip (or 'clip') silkscreen to the mask opening and not just to the copper pad. However, doing so can render silkscreen text unreadable. Being able to catch such occurrences, through DRC, allows you to manipulate offending silkscreen text prior to sending the board to manufacturing.

Constraints

• Clearance Checking Mode - choose a checking mode for the clearance:
  • Check Clearance To Exposed Copper - in this mode, clearance checking is between silkscreen (Top/Bottom Overlay layer) objects, and copper in component pads which is exposed through openings in the solder mask.
  • Check Clearance To Solder Mask Openings - in this mode, clearance checking is between silkscreen (Top/Bottom Overlay layer) objects, and solder mask openings created by objects that include a solder mask, such as pads, vias, or copper objects with the Solder Mask Expansion option enabled.
• Silkscreen To Object Minimum Clearance - specifies the minimum permissable clearance between a silkscreen object and either exposed copper, or solder mask openings, depending on the clearance checking mode chosen.

Rule Application

Online DRC and Batch DRC.

This rule defines the minimum clearance allowed between text and other objects on a silkscreen layer.

Constraints

Silk Text to Any Silk Object Clearance - specifies the minimum permissible clearance between any two silkscreen objects.

Rule Application

Online DRC and Batch DRC.

This rule operates at a net level in the design to flag any open-ended track/arc primitive, or open-ended track/arc that is terminated with a via, and thus forms an antenna.

Constraints

Net Antennae Tolerance - maximum permissible length for the stub of an open-ended track/arc primitive (or one that terminates in a via).

Rule Application

Online DRC and Batch DRC.

This rule defines the minimum clearance allowed from design objects that are fabricated, to edges of the board. Either a single clearance value can be specified for all object-to-edge possibilities, or different clearances for different pairings can be defined, through the use of a dedicated Minimum Clearance Matrix. The terms Board Outline and Board Edge are general names used interchangeably to describe the outer edge of the board. The term edge is defined in the table below the image. The Board Outline Clearance design rule checks object-to-edge clearances on the electrical and overlay (silkscreen) layers.

Constraints

• Minimum Clearance - the value for the minimum clearance required. A value entered here will be replicated across all cells in the Minimum Clearance Matrix. Conversely, when a different clearance value is entered for one or more object pairings in the matrix, the Minimum Clearance constraint will change to N/A, to reflect that a single clearance value is not being applied across the board.
• Minimum Clearance Matrix - provides the ability to fine tune clearances between the various object-to-edge clearance combinations in the design.

Working with the Clearance Matrix

Definition of clearance values in the matrix can be performed in the following ways:

• Single cell editing - to change the minimum clearance for a specific object pairing.
• Multi-cell editing - to change the minimum clearance for multiple object pairings:
  • Use Ctrl+Click, Shift+Click, and Click+Drag to select multiple cells in a column.
  • Use Shift+Click, and Click+Drag to select multiple contiguous cells in a row.
  • Use Click+Drag to select multiple contiguous cells across multiple rows and columns
  • Click on a row header to quickly select all cells in that row.
  • Click on a column header to quickly select all cells in that column.

With the required selection made (either a single cell or multiple cells), making a change to the current value is simply a case of typing the new value required. To submit the newly entered value, either click away on another call, or press Enter. All cells in the selection will be updated with the new value.

Rule Application

Online DRC, Batch DRC, interactive routing, and autorouting.

This rule specifies the distance two track segments can run in parallel, for a given separation.

Constraints

• Layer Checking - specifies where the two track segments to be checked should reside:
  • Same Layer - the track segments for the targeted nets are both on the same layer
  • Adjacent Layers - the track segments for the targeted nets are on adjacent layers.
• For a parallel gap of - specifies the parallel gap that should exist between two track segments before they can be considered for test. Parallel track segments with a gap of this value or less will be tested.
• The parallel limit is - specifies the maximum permissible parallel length of two track segments (on different nets), when the parallel gap constraint is observed over the entire length.

Rule Application

Online DRC and Batch DRC.

Note

This rule detects parallel track segments that are within the parallel gap setting, then adds all segment lengths that are in those nets. When the sum of these segment lengths exceeds the parallel limit, a DRC violation is flagged. A simple example is shown below.

This rule specifies the minimum and maximum lengths of a net.

Constraints

• Length Units - choose this option to define the length as a distance.
• Delay Units - choose this option to define the length as a time (how long the signal takes to travel along that length of route).
• Minimum - the value for the minimum permissible length of the net.
• Maximum - the value for the maximum permissible length of the net.

Rule Application

Online DRC and Batch DRC.

This rule specifies the allowable difference in net lengths. This rule is essential in a high-speed design, where the challenge is not just about how long it takes the signals to arrive (which is determined by their overall length), but how important it is that the specified signals arrives at the same time. Depending on the signal switching speeds, the function of the signal, and the materials used in the board, the allowed difference could be as much as 500mils, or as little as 1mil.

The set of nets being targeted is defined by the scope of the rule (as defined by its full query), with the reference length (the longest net in the set) being determined by the rule scope, in combination with the Constraints settings. Other targeted nets will pass the rule if their Current Length is:

(LongestLength - tolerance) ≤ CurrentLength ≤ LongestLength

Constraints

• Length Units - choose this option to define the length as a distance.
• Delay Units - choose this option to define the length as a time (how long the signal takes to travel along that length of route).
• Tolerance - specifies a length tolerance when comparing each net with the longest net in the set. Any net whose length does not lie within the specified tolerance is deemed to be too short and will have track added to it should the Equalize Net Lengths command be run.

• Source Target - this drop-down is only available when an xSignal class (or all xSignals of the design) is used as the rule scope. Select an xSignal from the drop-down to use its length as a target for other xSignals scoped by the rule. When an xSignal is selected as a source target, other targeted xSignals will pass the rule if their Current Length is:

  (TargetLength - tolerance) ≤ CurrentLength ≤ (TargetLength + tolerance)

• Group Matched Lengths - choose this option to check lengths between all nets targeted by the rule scope.
• Within Differential Pair Length - choose this option to check lengths between the nets in each differential pair targeted by the rule scope. Refer to the Notes section to learn more.

Rule Application

Online DRC, Batch DRC, the Equalize Net Lengths feature, interactive length tuning.

Notes

• The PCB Editor can add "accordion" sections to nets to equalize their lengths. Having defined the Matched Lengths rule, from the PCB document select Tools » Equalize Net Lengths . The matched lengths rule will be applied to the nets specified by the full query of the rule and accordion sections will be added to those whose length falls outside the permissible tolerance. The underlying algorithm that adds the accordion sections will only do so on vertical and horizontal tracks. If a net has been predominantly routed using 45° track segments, the possibility of successful equalization will be greatly reduced, depending upon the availability and extent of horizontal and vertical track on which to add the equalizing accordion lengths. If nets with such routing do exist, reroute them using short 45° track lengths and more orthogonal sections. The degree of success depends on the amount of space available for the accordion sections and the accordion style being used. The 90° style is the most compact and the 45° style is the least compact. Alternatively, use the Interactive Length Tuning command instead.
• When scoping a Matched Net Length rule for interactive tuning purposes:
  • For individual nets - define a class containing the nets that you wish to tune (Net, Differential Pair or xSignal class), and scope the rule to target that class. The length tuning tool will then find the longest net in that set of target nets and give you a valid range for the target nets of: (LongestLength - tolerance) ≤ CurrentLength ≤ LongestLength.
  • For differential pair nets - if there are multiple differential pairs and the design requires pair-to-pair matched net lengths, you will create two Matched Net Length rules. The first rule defines the pair-to-pair length matching requirements, and has the Constraint set to Group Matched Lengths. The second rule is to ensure the nets within each differential pair are within tolerance and has the Constraint set to Within Differential Pair Length. When this Constraint option is used, the software will detect all differential pairs targeted by the rule scope, and then compare the +ve and -ve members of each pair against each other.

This rule specifies the maximum permissible stub length for a net with a daisy chain topology.

Constraints

Maximum Stub Length - the value for the maximum stub length allowed.

Rule Application

Online DRC and Batch DRC.

This rule specifies whether vias can be placed under SMD pads.

Constraints

Allow Vias under SMD Pads - specifies whether vias can be placed under the pads of surface mount components.

Rule Application

Online DRC, Batch DRC, interactive routing, and autorouting.

This rule specifies the maximum number of vias permitted for each individual net in the current design.

Constraints

Maximum Via Count - the maximum number of vias permitted in each individual net falling under the defined scope of the rule.

Rule Application

Online DRC and Batch DRC.

A stub is the length of via or pad barrel that protrudes beyond the last-used signal layer that the via/pad connects on. Back drilling will be applied to suitable vias/pads in nets targeted by this rule, in accordance with the enabled side-of-board Layer checkboxes, and the back drill pairs defined on the Back Drills tab of the Layer Stack Manager.

As well as being used to define which vias/pads are to be considered for back drilling, during design rule checking this rule tests for via and pad stubs longer than the specified Max Stub Length, for all nets targeted by this rule (regardless of whether back drilling has been applied to that via or pad). This rule also specifies how much larger the drill size must be for vias and pads that are back drilled.

Constraints

• Max Stub Length - the maximum length of stub allowed. This setting is used to test for remaining stubs of this length or longer, it does not define the drill depth used for back drilling.
  • Top Layer - back drill vias/pads, in targeted nets, from the top side of the board.
  • Bottom Layer - back drill vias/pads, in targeted nets, from the bottom side of the board.
• Back Drill Oversize - the radial increase in size of the drill used for back drilling, over the original via/pad hole size.
  • Tolerance - allowable +ve and -ve tolerance allowed on this drill size, enter both as a positive number.

Rule Application

Batch DRC.

This rule specifies a continuous signal return path along the designated reference layer above or below the signals targeted. The return path can be created from fills, regions, and polygon pours placed on a signal layer or plane layers. 

Constraints

• Exclude Pad/Via Voids - when enabled, openings in the return path created by the clearance around pads and vias that belong to the targeted net(s), are not flagged as violations. 
• Minimum Gap to Return Path - indicates the minimum gap from the conductor edge to the outer edge of the return path. The check is applied along the entire length of the conductor. An error will be flagged if the gap is equal to or less than the Minimum Gap to Return Path value (default value is 0 mm).
• Impedance Profile - select the applicable impedance profile for the nets targeted by this rule. The profile specifies which layer(s) provide the return path for the targeted signals. Once the layer stack has been selected, the available signal layers and their respective reference layers, will be shown in the grid region of the dialog.

Rule Application

Batch DRC.

This rule can be used in the following ways:

• To specify a rectangular or polygonal region on the top side or the bottom side of the board, where components are either allowed in, or not allowed in.
• To define a named region (area) on the board, where the named region is then used to scope other design rules. When used in this way the room simply defines an area of the board. To restrict it in other ways, such as to a specific layer, include that in the Query of the rule. There is an example of a Routing Width rule that uses this approach in the image in the note, shown below.

Constraints

• Room Locked - allows you to lock the room in its current position within the design, preventing accidental movement either manually or by the Autoplacers. If you attempt to move the room when it has been locked, a warning dialog will appear asking whether you wish to go ahead with the move. The locked status of the room remains in force after such a manual-override movement.
• Components Locked - allows you to lock the position of components arranged within, and associated to, the room. If you attempt to move a component within a room when this option is enable, the room and all components within it, will move.
• Define button - enables you to define the area and location of the room. After clicking, you will return to the main design window, the cursor will change to a cross-hair and you will essentially enter room placement mode. Define the polygonal room as required and at the location required. The component membership for the room has to be defined afterwards, it is not created automatically if the room area is defined around placed components in the design.
• x1 and y1 - display the coordinates for the location of the lower-left corner of the room's bounding rectangle. These fields are non-editable; if placing the room from within the PCB Rules and Constraints Editor dialog, the Define button must be used.
• x2 and y2 - display the coordinates for the location of the upper-right corner of the room's bounding rectangle. These fields are non-editable; if placing the room from within the PCB Rules and Constraints Editor dialog, the Define button must be used.
• Layer - defines which side of the board the room is drawn on. The objects that the room contains do not need to be on the same layer, the condition of belonging in or not belonging in the room is established by the rule Query.
• Confinement Mode - specifies whether the components targeted by the scope (Full Query) of the rule are to be kept Inside the room or kept Outside of the room.

Rule Application

Online DRC and Batch DRC.

Notes

• A component can be scoped by multiple Room Definition rules. In this case, all rules are obeyed. Rule contentions are not possible.
• A room can only be placed graphically. To position a room at a specific location, place suitable Vertical, Horizontal, or Point (Snap) Guides, and enable snapping to Guides in the Properties panel (in Board mode). Learn more about Guides and configuring the PCB Grids System.
• The shape of a room can be edited graphically, or in the Properties panel when the room is selected. Click on a room to select it, then click and drag on a corner or edge vertex to resize it graphically. To edit a polygonal room, or perform polygonal-type edits on a rectangular room, use the Design » Rooms » Edit Polygonal Room Vertices command (or right-click on the room and run the command from the Room Actions sub-menu). Standard polygonal object editing techniques are used, including Shift+Spacebar to cycle through the vertex editing modes (Miter, Incurvate, Move). Keep an eye on the Status bar or Heads up display to check the current mode.

• If you need a complex room shape based on precise locations, the shape can be created as an outline by placing a sequence of lines (and arcs), and then selecting and converted this outline to a room by running the Tools » Convert » Create Room from Selected Primitives command. Note that the end points of adjoining track/arc segments must coincide for this command to correctly detect the shape. Hover the cursor over the image below to see the room.

  ❯ ❮

  

  

  Javascript
• As well as defining a room by clicking the Define button in the design rule, rooms can also be created/edited using the various commands available from the Design » Rooms sub-menu. When placing a room in the design using commands from the Design » Rooms sub-menu, the room can either be placed empty and components associated at a later stage, or it can be placed around components in the design, automatically associating them to the room:
  • When an empty room is placed in the design, components required to be placed in the room should be grouped together by creating a specific component class (Design » Classes). A Room Definition rule will automatically be created and assigned to the room, with an initial scope (Full Query) of All. Edit this query to target the specific component class previously defined. The components can then be moved to the room by running the Tools » Component Placement » Arrange Within Room command.
  • By placing a room around one or more components, so that they fall completely within its boundaries, the components will automatically be associated to the room. The scope (or query) for the room's definition rule depends on whether all components are part of an existing component class or not. If they are, then this component class will be used. If not, a new component class is created, with these components as its members. It is therefore possible to have multiple rooms, each with a scope that targets a particular component class, and have one or more mutual component members between those classes.
• Use the Create Room from selected components-based commands (Design » Rooms sub-menu) to automatically generate a Rectangular, Orthogonal or Non-Orthogonal shaped room, whose members are the selected components. A component class is automatically defined to include the selection. A room is then created, the Room Definition rule of which is defined to associate the created component class. The room will be sized accordingly, in order to fit all components in the selection, as defined by the limits of their bounding rectangles.
• Once components have been assigned to a room they move when the room is moved. To move a room without moving the components, temporarily disable the associated Room Definition rule.
• As well as being a design rule in its own right to contain or exclude components, a room can also be used to define the scope of another rule, such as Clearance, Height, Routing Width, Solder Mask Expansion, Power Plane Connections, and so on. As the room is to be used as an object rather than a rule, you can disable the rule, or set the query (rule scope) to False, as shown in the image below. The following two queries can be used when using a room object in another rules' scope definition:
  • TouchesRoom(RoomName) - use to find objects that are completely or partially within the room.
  • WithinRoom(RoomName) - use to find objects that are completely within the room.

  A Room can be used as a Query for another rule by referring to it by its Name, as shown above.

  Note that within the room, the routing width, the plane connection style, and the solder mask expansion have different values from the values outside of the room.

This rule specifies the minimum distance that components can be placed from each other. Component clearance includes clearance between 3D models used to define component bodies. In the absence of 3D bodies (or when the Check clearance by component boundary option is enabled in rule constraints), a closed contour formed by the primitives on the courtyard layer is used for rule checking. When there are no 3D Body objects or closed contours on the Courtyard layer defined, the bounding rectangle formed by primitives on the silk, copper and mechanical layers (excluding .Designator and .Comment text strings) is used.

Component clearance is calculated using accurate 3D meshing to define shape and contour for the component through its associated 3D body objects. These may be extruded 2D shapes. It is evident that using 3D bodies provides greatest accuracy when it comes to clearance checking, particularly in the vertical sense and in the context of complex component shapes.

Constraints

• Vertical Clearance Mode – two modes for specifying vertical clearance are available:
  • Infinite – clearance checking is performed using a value representing infinity. This means that any components placed above or below will be in violation. An example of use would be a board that has an adjustment mechanism that must remain accessible. Using this rule on that component will cause a violation against any components that protrude into the area above or below the component.
  • Specified – clearance checking is performed using the exact shape defined by the component 3D bodies or component footprint properties. When using 3D bodies, it is possible to have an acceptable overhang between one component over another, provided they are not in violation. With this mode enabled, the following constraint becomes available:
    • Minimum Vertical Clearance – the value for the minimum permissible clearance, in the vertical sense, between placed components in the design.
• Minimum Horizontal Clearance – the value for the minimum permissible clearance, in the horizontal plane, between placed components in the design.

• Show actual violation distances – enable this option to show lines between the points of greatest violation between components. The distance of the line is displayed and can be useful in calculating the distance required to move an object to resolve the violation.

  Enabling the Show actual violation distances option may reduce performance on some computer systems.
• Do not check components without 3D body – enable this option to exclude components without a 3D Body from being clearance checked by this rule.
• Check clearance by component boundary – enable this option to use the component boundary for component clearance checking.

Rule Application

Online DRC and Batch DRC.

Notes

• An extruded (simple) 3D body is a polygonal shaped object that can be placed in a library component or a PCB document, on any enabled mechanical layer. In a component footprint, it can be used to specifically define the physical size and shape of a component in the X, Y and Z-axes.
• Multiple 3D body primitives may be used to define shapes of any complexity. This can prove especially useful in the vertical sense, as it allows you to vary the height of a component in different regions of that component.
• To allow collision of the components scoped by a Component Clearance design rule (i.e. to not report component collision during design rule check), set both Minimum Horizontal Clearance and Minimum Vertical Clearance option values to 0.

The rule is not currently observed by the DRC tool.

This rule specifies the layers on which components can be placed.

Constraints

• Permitted Layers - the layers permitted to be used when placing components. The following layer options are available:
  • Top Layer - allow component placement on the top layer.
  • Bottom Layer - allow component placement on the bottom layer.

Rule Application

Batch DRC.

Note

The rule acts as a test when performing a Batch DRC, to ensure components - targeted by the query expression of the rule's scope - are being placed only on a permitted layer. Parameters specified for components on the schematic, and that have been brought across into footprints on the PCB, can be used to great effect for this very purpose. For example, to check that components that do not support wave soldering are not placed on the bottom layer, a rule of this type can be defined. If we consider a component parameter, SupportsWaveSolder, has been defined for components and brought across as parameters of the footprints in the PCB, then the rule scope might be:

CompParameterValue('SupportsWaveSolder') <> 'Yes'

and only the Top Layer constraint would be permitted, with the Bottom Layer constraint disabled.

The rule is not currently observed by the DRC tool.

This rule specifies height restrictions for components placed within the design.

Constraints

• Minimum - the value for the minimum permissible component height.
• Preferred - the value for the preferred component height.
• Maximum - the value for the maximum permissible component height.

Rule Application

The Preferred setting is obeyed when displaying the board in 3D. The Minimum and Maximum settings are obeyed by the Online DRC and Batch DRC.

Notes

• The height property for a component is defined in its associated properties dialog.
• A component class can be created and used in the scope definition for a height rule, in order to flag any member components whose height violates the specified height constraint criteria of the rule.

This rule specifies the characteristics of the stimulus signal used when performing a signal integrity analysis on the design. This is the signal that is injected at each output pin on the net under test. The worst-case result is returned during design rule checking.

Constraints

• Stimulus Kind - specifies the type of stimulus signal that is injected during signal integrity analysis. The following stimulus types are available:
  • Constant Level - the stimulus signal remains at a constant voltage - either High or Low - depending on the chosen Start Level option
  • Single Pulse - the stimulus signal is a single pulse, whose characteristics are defined by the Start Level, Start Time and Stop Time options
  • Periodic Pulse - the stimulus signal is a continuous pulse train, whose characteristics are defined by the Start Level, Start Time, Stop Time and Period Time options.
• Start Level - specifies the voltage level used for the Constant Level stimulus signal, or the initial voltage level for the pulse-based stimulus signals. The following levels are available:
  • Low Level - defined as the LOW level voltage for the output pin - dependent on the model used for the pin
  • High Level - defined as the HIGH level voltage for the output pin - dependent on the model used for the pin.
• Start Time (s) - the start time for a pulse-based stimulus signal. Used in calculating the width of the pulse.
• Stop Time (s) - the stop time for a pulse-based stimulus signal. Used in calculating the width of the pulse.
• Period Time (s) - the time between pulses in a periodic pulse train stimulus signal. After the period time has elapsed, another identical pulse of width Stop Time - Start Time is injected.

Rule Application

Batch DRC and during Signal Integrity analysis.

Note

When performing a Crosstalk analysis, an Aggressor net will be injected with the stimulus defined in the Stimulus design rule, the LOW and HIGH levels of which are dependent on the model used for the driving output pin. A Victim net will get a Constant Low level voltage injected into it, with the level again being dependent on the model used for the output pin.

This rule specifies the maximum allowable overshoot (ringing below the base value) on the falling edge of the signal.

Constraints

Maximum (Volts) - the value for the maximum permissible overshoot on the falling edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum allowable overshoot (ringing above the top value) on the rising edge of the signal.

Constraints

Maximum (Volts) - the value for the maximum permissible overshoot on the rising edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum allowable undershoot (ringing above the base value) on the falling edge of the signal.

Constraints

Maximum (Volts) - the value for the maximum permissible undershoot on the falling edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum allowable undershoot (ringing below the top value) on the rising edge of the signal.

Constraints

Maximum (Volts) - the value for the maximum permissible undershoot on the rising edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the minimum and maximum net impedance allowed. Net impedance is a function of the conductor geometry and conductivity, the surrounding dielectric material (the board base material, multi-layer insulation, solder mask, etc) and the physical geometry of the board (distance to other conductors in the z-plane).

Constraints

• Minimum (Ohms) - the value for the minimum permissible net impedance.
• Maximum (Ohms) - the value for the maximum permissible net impedance.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the minimum voltage level that a signal can settle to in the high state (the top value).

Constraints

Minimum (Volts) - the value for the minimum permissible top value voltage.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum voltage level that a signal can settle to in the low state (the base value).

Constraints

Maximum (Volts) - the value for the maximum permissible base value voltage.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum allowable flight time on signal rising edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes to drive the signal on the net to the threshold voltage (marking the transition from signal LOW to signal HIGH), less the time it would take to drive a reference load (connected directly to the output) to the threshold voltage.

Constraints

Maximum (seconds) - the value for the maximum permissible flight time on the rising edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum allowable flight time on signal falling edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes for the signal on the net to fall to the threshold voltage (marking the transition from signal HIGH to signal LOW), less the time it would take for a reference load (connected directly to the output) to fall to the threshold voltage.

Constraints

Maximum (seconds) - the value for the maximum permissible flight time on the falling edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH).

Constraints

Maximum (seconds) - the value for the maximum permissible rising edge slope time.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule specifies the maximum allowable slope time on the falling edge of the signal. Falling edge slope is the time it takes for a signal to fall from the threshold voltage (VT), to a valid low (VIL). Constraints.

Constraints

Maximum (seconds) - the value for the maximum permissible falling edge slope time.

Rule Application

Batch DRC and during Signal Integrity analysis.

This rule identifies a supply net and specifies its voltage (or set of nets using the net class scope).

Constraints

Voltage - the voltage value for the net(s) falling under the scope (full query) of the rule.

Rule Application

Batch DRC and during Signal Integrity analysis.

Note

The supply net(s) can be specified by choosing the Net or Net Class from the drop-down field in the Where The Object Matches region of the PCB Rules and Constraints Editor dialog, and then choosing the required net or net class from the corresponding secondary drop-down list. The corresponding Full Query for the rules' scope will be as follows: InNet('NetName') - for a single net; InNetClass('NetClassName') - for a net class.